Joseph E Palumbo

US Patent:

6990648, Jan 24, 2006

Filed:

Apr 4, 2003

Appl. No.:

10/408203

Inventors:

Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 9, 716 10, 716 5, 716 7, 716 2

Abstract:

A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without any pin to pin segment increasing in length. Circuits placed within the region of wiring congestion are identified and examined to determine the circuits they connect to. The placements of the connected circuits are analyzed to derive a rectangle of connectivity. Each of the originally identified circuits are then checked to determine if they are placed within their associated rectangle of connectivity. If not, the distance between the circuit and rectangle is calculated along with a recommended placement location, both of which are reported along with the circuit. The recommended placement location is a point along the border of the rectangle such that replacement of the circuit at the location reduces all circuit net lengths without increasing any pin to pin segment. In this way, wiring tracks are freed up without any potential for increased path delays.

US Patent:

7827513, Nov 2, 2010

Filed:

Oct 11, 2007

Appl. No.:

11/870728

Inventors:

Joseph J. Palumbo - Poughkeepsie NY, US
Christopher J. Berry - Hudson NY, US
Adam R. Jalkowski - Wyoming PA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 10, 716 14

Abstract:

A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

US Patent:

8010922, Aug 30, 2011

Filed:

Feb 18, 2008

Appl. No.:

12/032762

Inventors:

Frank Malgioglio - Hopewell Junction NY, US
Adam R. Jatkowski - Wyoming PA, US
Brian A. Lasseter - Austin TX, US
Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716114, 716113

Abstract:

Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.