Joseph J Palumbo

US Patent:

6904585, Jun 7, 2005

Filed:

Apr 4, 2003

Appl. No.:

10/408206

Inventors:

Mark A. Brittain - Pflugerville TX, US
Kenneth D. Klapproth - Austin TX, US
Vu T. Le - Poughkeepsie NY, US
Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716 13, 716 12, 716 14, 716 5

Abstract:

A method for identifying and modifying, in a VLSI chip design, wire routes within a region of wiring congestion that can be routed around that region without inducing timing violations by the insertion and proper placement of inverters. Circuits and nets are examined in the vicinity of the wiring congestion to determine those nets with high potential to drive a route outside the region. Circuit locations are analyzed to determine if the net connecting them creates a path through the region of wiring congestion. Timing slacks are derived from the timing reports for such nets and compared against a timing value representing the additional delay of using an inverter pair to drive the wire route outside the region of wiring congestion. If a net has sufficient timing slack, it is buffered with an inverter pair which is then placed in a manner as to force the wire routes for the modified path around the region of wiring congestion, thereby reducing the wire utilization within the region.

US Patent:

6990648, Jan 24, 2006

Filed:

Apr 4, 2003

Appl. No.:

10/408203

Inventors:

Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 9, 716 10, 716 5, 716 7, 716 2

Abstract:

A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without any pin to pin segment increasing in length. Circuits placed within the region of wiring congestion are identified and examined to determine the circuits they connect to. The placements of the connected circuits are analyzed to derive a rectangle of connectivity. Each of the originally identified circuits are then checked to determine if they are placed within their associated rectangle of connectivity. If not, the distance between the circuit and rectangle is calculated along with a recommended placement location, both of which are reported along with the circuit. The recommended placement location is a point along the border of the rectangle such that replacement of the circuit at the location reduces all circuit net lengths without increasing any pin to pin segment. In this way, wiring tracks are freed up without any potential for increased path delays.

US Patent:

7568176, Jul 28, 2009

Filed:

Jun 4, 2007

Appl. No.:

11/757457

Inventors:

Adam R. Jatkowski - Wyoming PA, US
Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 7, 716 8

Abstract:

A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.

US Patent:

7827513, Nov 2, 2010

Filed:

Oct 11, 2007

Appl. No.:

11/870728

Inventors:

Joseph J. Palumbo - Poughkeepsie NY, US
Christopher J. Berry - Hudson NY, US
Adam R. Jalkowski - Wyoming PA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 10, 716 14

Abstract:

A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

US Patent:

8010922, Aug 30, 2011

Filed:

Feb 18, 2008

Appl. No.:

12/032762

Inventors:

Frank Malgioglio - Hopewell Junction NY, US
Adam R. Jatkowski - Wyoming PA, US
Brian A. Lasseter - Austin TX, US
Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716114, 716113

Abstract:

Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

US Patent:

20130326456, Dec 5, 2013

Filed:

Jun 4, 2012

Appl. No.:

13/488065

Inventors:

Charles Jay Alpert - Austin TX, US
Joseph Nicolas Kozhaya - Morrisville NC, US
Zhuo Li - Cedar Park TX, US
Joseph J Palumbo - Poughkeepsie NY, US
Haifeng Qian - White Plains NY, US
Phillip John Restle - Katonah NY, US
Chin Ngai Sze - Austin TX, US
Ying Zhou - , US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716122

Abstract:

An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

US Patent:

20180232481, Aug 16, 2018

Filed:

Feb 13, 2017

Appl. No.:

15/431061

Inventors:

- Armonk NY, US
Adam R. Jatkowski - Wyoming PA, US
Frank Malgioglio - Hopewell Junction NY, US
Ryan M. Nett - Austin TX, US
Joseph J. Palumbo - Poughkeepsie NY, US
Sean Salisbury - Poughkeepsie NY, US

International Classification:

G06F 17/50

Abstract:

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

US Patent:

20170132349, May 11, 2017

Filed:

Nov 10, 2015

Appl. No.:

14/936920

Inventors:

- Armonk NY, US
Randall J. Darden - Ridgedale MO, US
Adam R. Jatkowski - Bethlehem PA, US
Joseph J. Palumbo - Poughkeepsie NY, US
Shyam Ramji - Lagrangeville NY, US
Sourav Saha - Barrackpur, IN
Timothy A. Schell - San Diego CA, US
Eddy St. Juste - Bridgeport CT, US

International Classification:

G06F 17/50

Abstract:

A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.