Joseph L Petty

US Patent:

62336436, May 15, 2001

Filed:

Jun 23, 1999

Appl. No.:

9/338611

Inventors:

Lawrence P. Andrews - Boca Raton FL
Richard Clyde Beckman - Boca Raton FL
Robert Chih-Tsin Eng - Boca Raton FL
Judith Marie Linger - Delray Beach FL
Joseph C. Petty - Boca Raton FL
John Claude Sinibaldi - Pompano Beach FL
Gary L. Turbeville - Boca Raton FL
Kevin Bradley Williams - Plantation FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1338

US Classification:

710131

Abstract:

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

US Patent:

60651318, May 16, 2000

Filed:

Nov 26, 1997

Appl. No.:

8/979530

Inventors:

Lawrence P. Andrews - Boca Raton FL
Richard C. Beckman - Boca Raton FL
Joseph C. Petty - Boca Raton FL
John C. Sinibaldi - Pompano Beach FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 108

US Classification:

713600

Abstract:

The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.