Joseph H Rawlings

US Patent:

56528655, Jul 29, 1997

Filed:

May 31, 1995

Appl. No.:

8/458984

Inventors:

Joseph H. Rawlings - Portland OR

International Classification:

G06F 1200
G06F 1300

US Classification:

39549702

Abstract:

A computer file system mechanism to use data port storage efficiently wherein lost or unused storage space is minimized and use of available storage maximized. The data port file system may be used as an augmentation of existing file system mechanisms or in complete replacement thereof. The data port file system may be implemented such that the information required to maintain the file system is always updated to the data port or such that the information required to maintain the file system is always located in system memory during computer operations. The data port file system may be implemented such that both methods are used.

US Patent:

59876271, Nov 16, 1999

Filed:

Oct 27, 1992

Appl. No.:

7/968044

Inventors:

Joseph H. Rawlings - Portland OR

International Classification:

G06F 1100

US Classification:

714 48

Abstract:

An apparatus called a DataPort is disclosed for use in conjunction with a computer. The DataPort includes a private memory comprised of a high-speed, solid-state random access memory array. A public memory comprising a series of registers serves as an intermediary between the private memory array and a computer CPU local bus for memory access operations. The public memory includes staging registers which are used for conversion between the CPU local bus word size and the internal private memory word size as may be necessary, including pipelining as required. The DataPort also generates error correction codes (ECC) and stores the correction codes in the private memory, interleaved with data received from the CPU local bus, and checks the ECC codes to detect errors when data is read back out to the bus. The DataPort has the advantages of providing a high-speed, variable packet length, error-corrected access to a memory array at the CPU local bus operating speed, so that the device can be used with no wait states for improved throughput in a computer system.