Joseph J Smart

US Patent:

20150279945, Oct 1, 2015

Filed:

Oct 25, 2013

Appl. No.:

14/432721

Inventors:

Daniel FRANCIS - Oakland CA, US
Dubravko BABIC - Santa Clara CA, US
Felix EJECKAM - San Francisco CA, US
Quentin DIDUCK - Ithaca NY, US
Joseph SMART - Mooresville NC, US
Kristopher MATTHEWS - San Francisco CA, US
Frank LOWE - Phoenix AZ, US
- Santa Clara CA, US

International Classification:

H01L 29/32
H01L 29/20
H01L 29/04
H01L 29/16
H01L 21/02
H01L 21/683

Abstract:

Methods for manufacturing semiconductor wafer structures are described which exhibit improved lifetime and reliability. The methods comprise transferring an active semiconductor layer structure from a native non-lattice-matched semiconductor growth substrate to a working substrate, wherein strain-matching layers, and optionally a portion of the active semiconductor layer structure, are removed. In certain embodiment, the process of attaching the active semiconductor layer structure to the working substrate includes annealing at an elevated temperature for a specified time. The methods as described herein can be used to fabricate working semiconductor wafer structures which have a low concentration of dislocation defects throughout the active semiconductor layer structure and which do not comprise highly dislocated strain-matching layers which are present in the native semiconductor growth substrate