Joseph P Sousa

US Patent:

6522187, Feb 18, 2003

Filed:

Mar 12, 2001

Appl. No.:

09/804348

Inventors:

Joseph L. Sousa - Lawrence MA

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 1716

US Classification:

327391, 327437

Abstract:

A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.

US Patent:

7683695, Mar 23, 2010

Filed:

Aug 18, 2006

Appl. No.:

11/506338

Inventors:

Joseph L. Sousa - Lawrence MA, US
David M. Thomas - Colorado Springs CO, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 17/16

US Classification:

327382, 327362

Abstract:

Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.

US Patent:

7916057, Mar 29, 2011

Filed:

Apr 27, 2009

Appl. No.:

12/430482

Inventors:

Andrew Joseph Thomas - Arlington MA, US
Joseph Luis Sousa - Lawrence MA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03M 1/66

US Classification:

341144, 341150, 341172

Abstract:

A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.

US Patent:

8018370, Sep 13, 2011

Filed:

Feb 1, 2010

Appl. No.:

12/698020

Inventors:

Andrew J. Thomas - Arlington MA, US
Joseph L. Sousa - Lawrence MA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03M 1/34

US Classification:

341162, 341118, 341120, 341155, 341161, 341163

Abstract:

A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.

US Patent:

8319545, Nov 27, 2012

Filed:

Feb 24, 2010

Appl. No.:

12/711828

Inventors:

Joseph Sousa - Lawrence MA, US
Andrew Thomas - Arlington MA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

G05F 1/10

US Classification:

327536

Abstract:

Circuits and methods for maintaining a substantially constant input and output current for a charge pump circuit are provided which reduce current variation during switching intervals. The charge pump circuitry of the present invention maintains a current flow path from a current source to the charge pump output which minimizes or eliminates spikes normally associated with the switching intervals.

US Patent:

6084440, Jul 4, 2000

Filed:

Apr 15, 1998

Appl. No.:

9/060561

Inventors:

Joseph Luis Sousa - Lawrence MA

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

G11C 2702

US Classification:

327 94

Abstract:

The circuits and methods of the present invention provide sample and hold circuits that incorporate an auxiliary sampling leg that cancels distortion produced in a main sampling leg of the sample and hold circuit. The auxiliary sampling leg of the circuit produces canceling distortion that is proportionally larger than the distortion produced in the main sampling leg. The distortion in the auxiliary sampling leg is then reduced in size so that the canceling distortion becomes proportionally equal to the distortion in the main sampling leg. Finally, the proportionally equal canceling distortion of the auxiliary sampling leg is subtracted from the distortion of the main sampling leg so that substantially all of the distortion is canceled out while retaining a substantial portion of the input signal.

US Patent:

58315624, Nov 3, 1998

Filed:

Jul 12, 1996

Appl. No.:

8/678976

Inventors:

Jeffrey B. Van Auken - Littleton MA
Joseph L. Sousa - Lawrence MA

Assignee:

Sipex Corporation - Billerica MA

International Classification:

H03M 138

US Classification:

341122

Abstract:

A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors. Each of the common mode capacitors has an output terminal electrically coupled to a reference voltage and an input terminal electrically coupled to the input terminal of a different differential capacitor.

US Patent:

56380720, Jun 10, 1997

Filed:

Dec 7, 1994

Appl. No.:

8/350645

Inventors:

Jeffrey B. Van Auken - Littleton MA
Joseph L. Sousa - Lawrence MA

Assignee:

Sipex Corporation - Billerica MA

International Classification:

H03M 100

US Classification:

341141

Abstract:

A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.