Joseph C Yoder

US Patent:

6629276, Sep 30, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/559660

Inventors:

Joseph A. Hoffman - Chandler AZ
Joseph W. Yoder - Oakton VA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

G01R 3128

US Classification:

714726, 327144

Abstract:

A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.