Joshua D Conner

US Patent:

6728856, Apr 27, 2004

Filed:

Jun 1, 2001

Appl. No.:

09/870648

Inventors:

James H. Grosbach - Scottsdale AZ
Joshua M. Conner - Apache Junction AZ
Michael Catherwood - Pepperell MA

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 1202

US Classification:

711202

Abstract:

A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor.

US Patent:

6985986, Jan 10, 2006

Filed:

Jun 1, 2001

Appl. No.:

09/870447

Inventors:

Brian Boles - Mesa AZ, US
Joseph W. Triece - Phoenix AZ, US
Joshua M. Conner - Apache Junction AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 13/24
G06F 9/44

US Classification:

710262, 710260, 712244

Abstract:

A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.

US Patent:

7203818, Apr 10, 2007

Filed:

Mar 9, 2004

Appl. No.:

10/796771

Inventors:

Edward Brian Boles - Mesa AZ, US
Rodney Jay Drake - Gilbert AZ, US
Darrel Ray Johansen - Tempe AZ, US
Sumit K. Mitra - Tempe AZ, US
Randy Yach - Phoenix AZ, US
James Grosbach - Scottsdale AZ, US
Joshua M. Conner - Apache Junction AZ, US
Joseph W. Triece - Phoenix AZ, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G06F 12/00
G06F 15/00

US Classification:

712220, 711 5

Abstract:

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

US Patent:

7401176, Jul 15, 2008

Filed:

Oct 20, 2004

Appl. No.:

10/969513

Inventors:

Joshua M. Conner - Apache Junction AZ, US
James H. Grosbach - Scottsdale AZ, US
Joseph W. Triece - Phoenix AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 12/00

US Classification:

711 5, 712208, 712220

Abstract:

Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.

US Patent:

20030005269, Jan 2, 2003

Filed:

Jun 1, 2001

Appl. No.:

09/870458

Inventors:

Joshua Conner - Apache Junction AZ, US
John Elliot - Chandler AZ, US
Michael Catherwood - Pepperell MA, US
Brian Fall - Chandler AZ, US
Brian Boles - Mesa AZ, US

International Classification:

G06F009/00

US Classification:

712/223000

Abstract:

A processor configuration for processing multi-precision shift instructions is provided. The multi-precision shift instructions are executed following a previous shift instruction of the same increment, such as a logical or arithmetic left or right shift operation. The first shift instruction shifts a first memory word by the shift increment and stores this shifted value into memory. The second, and any subsequent, multi-precision shift instruction shifts the next memory word by the shift increment and concatenates the bits shifted out of the previously shifted memory word into bit positions of the memory word presently being shifted. This concatenated value is then stored back to memory and forms another part of the multi-precision shifted value.