Joshua Michael Howard

US Patent:

20200321446, Oct 8, 2020

Filed:

Sep 28, 2017

Appl. No.:

16/635739

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Joshua M. HOWARD - Portland OR, US
Ian A. YOUNG - Portland OR, US
Daniel H. MORRIS - Hillsboro OR, US

International Classification:

H01L 29/66
H01L 29/51

Abstract:

Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side

US Patent:

20200235243, Jul 23, 2020

Filed:

Sep 29, 2017

Appl. No.:

16/640043

Inventors:

- Santa Clara CA, US
Joshua M. Howard - Portland OR, US
Seiyon Kim - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 29/78
H01L 49/02
H01L 29/51

Abstract:

Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

US Patent:

20200203358, Jun 25, 2020

Filed:

Sep 27, 2017

Appl. No.:

16/642358

Inventors:

- Santa Clara CA, US
Joshua M. Howard - Portland OR, US
Seiyon Kim - Portland OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/11507
H01L 23/528
H01L 23/522
H01L 27/1159
H01L 49/02
H01L 29/78
H01L 29/51

Abstract:

Described is an apparatus which comprises: a first layer comprising a metal; a second layer comprising a first para-electric material, the second layer adjacent to the first layer; and a third layer comprising a second para-electric material, the third layer adjacent to the second layer, wherein the first para-electric material is different from the second para-electric material.

US Patent:

20190378845, Dec 12, 2019

Filed:

Mar 22, 2017

Appl. No.:

16/487417

Inventors:

- Santa Clara CA, US
Uygar E. Avci - Portland OR, US
Joshua M. Howard - Portland OR, US
Ian A. Young - Portland OR, US
Daniel H. Morris - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/1159
H01L 27/11592
H01L 21/28

Abstract:

Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.