Joshua Lindner - Canton MA, US Gary Lai - Sunnyvale CA, US Bradley Taylor - Oakland CA, US Peter Lam - Santa Clara CA, US Mark Rollins - Stittsville, CA Vladimir Dinkevich - Mountain View CA, US Craig Greenberg - Sunnyvale CA, US Christopher Phillips - San Jose CA, US Hsin Wang - Fremont CA, US
International Classification:
G06F015/00
US Classification:
712/037000, 712/229000
Abstract:
A reconfigurable chip is described using a reconfigurable functional unit including a shifter unit, arithmetic logic unit and multiplexers. The data path units are interconnected to other data path units. The interconnection is preferably done by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. In a preferred embodiment the reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable functional unit instructions preferably are stored in a reconfigurable functional unit instruction memory which is addressed by a state machine on the chip.
Gary Lai - Sunnyvale CA, US Joshua Lindner - Malden MA, US
International Classification:
G06F007/38 H03K019/177 G06F007/52
US Classification:
708/620000
Abstract:
A multiplication block for a reconfigurable chip includes multiple multiplication units and a group of the selectable adder units operably interconnectable with the multiplication units. The adder units can be selectively connected for different configurations. The multiplication block is preferably controlled by an instruction which can put the multiplication block into different configurations.
- Santa Clara CA, US Joshua James Lindner - Billerica MA, US Neil N. Marketkar - Boston MA, US Kai Troester - Pepperell MA, US Emil Talpes - San Mateo CA, US Ashok Tirupathy Venkatachar - Fremont CA, US
International Classification:
G06F 9/38
Abstract:
Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
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