Joshua W Randall

Address:

3816 Winslow Dr, Fort Worth, TX 76109

VIN:

1GTHK636X9F188388

Make:

GMC

Model:

SIERRA 2500HD

Year:

2009

US Patent:

20210374059, Dec 2, 2021

Filed:

May 27, 2020

Appl. No.:

16/884359

Inventors:

- Cambridge, GB
Tiago Rogerio Muck - Austin TX, US
Joshua Randall - Austin TX, US
Alejandro Rico Carro - Austin TX, US
Bruce James Mathewson - Papworth Everard, GB

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 12/0842
G06F 12/0875

Abstract:

A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.

US Patent:

20210064371, Mar 4, 2021

Filed:

Aug 26, 2019

Appl. No.:

16/550644

Inventors:

- Cambridge, GB
Joshua Randall - Austin TX, US
Jose Alberto Joao - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 9/30
G06F 9/52
G06F 9/48
G06F 9/50
G06F 12/0842

Abstract:

A method and apparatus for application thread prioritization to mitigate the effects of operating system noise is disclosed. The method generally includes executing in parallel a plurality of application threads of a parallel application. An interrupt condition of an application thread of the plurality of application threads is detected. A priority of the interrupted application thread is changed relative to priorities of one or more other application threads of the plurality of application threads, and control is returned to the interrupted application thread after the interrupt condition. The interrupted application thread then resumes execution in accordance with the changed priority.

US Patent:

20190102310, Apr 4, 2019

Filed:

Oct 2, 2017

Appl. No.:

15/722350

Inventors:

- Cambridge, GB
Joshua Randall - Austin TX, US
Wendy Arnott Elsasser - Austin TX, US

Assignee:

ARM LTD - Cambridge

International Classification:

G06F 12/0875
G06F 12/0811

Abstract:

A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.