Judith F Allen

US Patent:

6560137, May 6, 2003

Filed:

Jan 16, 2001

Appl. No.:

09/764223

Inventors:

Judith E. Allen - Monument CO
Lark E. Lehman - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 1122

US Classification:

365145, 365205, 36518521, 3651852, 365207

Abstract:

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

US Patent:

6856573, Feb 15, 2005

Filed:

Mar 13, 2003

Appl. No.:

10/389276

Inventors:

Judith E. Allen - Monument CO, US
Dennis R. Wilson - Colorado Springs CO, US
Joseph Perkalis - Colorado Springs CO, US

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C007/00

US Classification:

36523006, 365145

Abstract:

A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a fist bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

US Patent:

20050122765, Jun 9, 2005

Filed:

Nov 18, 2004

Appl. No.:

10/993202

Inventors:

Judith Allen - Monument CO, US
Dennis Wilson - Woodland Park CO, US
William Kraus - Palmer Lake CO, US
Lark Lehman - Monument CO, US

International Classification:

G11C011/22

US Classification:

365145000

Abstract:

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

US Patent:

60287837, Feb 22, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/970520

Inventors:

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 700

US Classification:

365145

Abstract:

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

US Patent:

59869194, Nov 16, 1999

Filed:

Nov 14, 1997

Appl. No.:

8/970518

Inventors:

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 700

US Classification:

365145

Abstract:

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

US Patent:

58927280, Apr 6, 1999

Filed:

Nov 14, 1997

Appl. No.:

8/970454

Inventors:

Judith E. Allen - Monument CO
Dennis R. Wilson - Colorado Springs CO
Joseph J. Perkalis - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 700

US Classification:

36523006

Abstract:

A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

US Patent:

62527932, Jun 26, 2001

Filed:

Sep 15, 2000

Appl. No.:

9/663121

Inventors:

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 700

US Classification:

365145

Abstract:

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

US Patent:

6185123, Feb 6, 2001

Filed:

Dec 17, 1999

Appl. No.:

9/465724

Inventors:

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G11C 700

US Classification:

365145

Abstract:

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.