Judith Sultenfuss Archer

US Patent:

60339314, Mar 7, 2000

Filed:

Jan 18, 1999

Appl. No.:

9/232527

Inventors:

Emily Ellen Hoffman - Carrollton TX
Judith Sultenfuss Archer - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2160

US Classification:

438109

Abstract:

A three-dimensional microchip circuit assembly process, wherein a three-layer dry adhesive film sandwich is used to prepare a stacked circuit cube.

US Patent:

58922873, Apr 6, 1999

Filed:

Aug 18, 1997

Appl. No.:

8/912508

Inventors:

Emily Ellen Hoffman - Carrollton TX
Judith Sultenfuss Archer - Dallas TX

Assignee:

Texas Instruments - Dallas TX

International Classification:

H01L 2348

US Classification:

257777

Abstract:

A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.

US Patent:

60690267, May 30, 2000

Filed:

Aug 18, 1997

Appl. No.:

8/912266

Inventors:

Robert E. Terrill - Carrollton TX
Judith Sultenfuss Archer - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2306

US Classification:

438109

Abstract:

This invention relates to the fabrication and assembly of semiconductor chips, substrates, and modules, and more particularly to methods and apparatus for achieving flexible, low-cost manufacturing. Commercial and military systems today are placing increasing demands on flexible application and reliable operation, as well as on simplified manufacturing.

US Patent:

6303977, Oct 16, 2001

Filed:

Dec 2, 1999

Appl. No.:

9/453135

Inventors:

Walter H. Schroen - Dallas TX
Judith S. Archer - Dallas TX
Robert E. Terrill - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2980

US Classification:

257635

Abstract:

A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic. Positioning a plurality of said chips on a support in a deposition apparatus and preferably using chemical vapor deposition or sputtering techniques, a layer, or a sandwich of layers, of moisture-impermeable material is deposited on all edge sides simultaneously while preventing deposition of said material on at least portion of the exposed active or passive surfaces.