Judith Hurst Mccullen from 64 Briar Ln, Essex Junction, VT 05452, age 64, Phone: 8028789794

Us Patents

Process And System For Maintaining 3 Sigma Process Tolerance For Parasitic Extraction With On-The-Fly Biasing
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US Patent:

6430729, Aug 6, 2002
Filed:

Jan 31, 2000
Appl. No.:

09/494975
Inventors:

L. William Dewey - Wappingers Falls NY
Peter A. Habitz - Hinesburg VT
Judith H. McCullen - Essex Junction VT
Edward W. Seibert - Richmond VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1750
US Classification:

716 4
Abstract:

A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.

Method Of Performing Parasitic Extraction For A Multi-Fingered Transistor
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US Patent:

6519752, Feb 11, 2003
Filed:

Apr 28, 2000
Appl. No.:

09/561096
Inventors:

William C. Bakker - Poughkeepsie NY
Peter A. Habitz - Hinesburg VT
Judith H. McCullen - Essex Junction VT
Edward W. Seibert - Richmond VT
Michael J. Sullivan - Essex Junction VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1750
US Classification:

716 14
Abstract:

A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.

Device Modeling For Proximity Effects
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US Patent:

7302376, Nov 27, 2007
Filed:

Feb 25, 2003
Appl. No.:

10/248853
Inventors:

Eric Adler - Jericho VT, US
Serge Biesemans - Mount Kisco NY, US
Micah S. Galland - Essex Junction VT, US
Terence B. Hook - Jericho VT, US
Judith H. McCullen - Essex Junction VT, US
Eric S. Phipps - Winston-Salem NC, US
James A. Slinkman - Montpelier VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

703 14
Abstract:

A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Methodology For Layout-Based Modulation And Optimization Of Nitride Liner Stress Effect In Compact Models
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US Patent:

7337420, Feb 26, 2008
Filed:

Jul 29, 2005
Appl. No.:

11/193711
Inventors:

Dureseti Chidambarrao - Weston CT, US
Donald L. Jordan - Weybridge VT, US
Judith H. McCullen - Essex Junction VT, US
David M. Onsongo - Newburgh NY, US
Tina Wagner - Newburgh NY, US
Richard Q. Williams - Essex Junction VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716 8, 716 9, 716 1, 716 2
Abstract:

System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

Integrated Circuit Diagnosing Method, System, And Program Product
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US Patent:

7503021, Mar 10, 2009
Filed:

Jun 16, 2005
Appl. No.:

11/160266
Inventors:

Matt Boucher - Colchester VT, US
John M. Cohn - Richmond VT, US
Richard Dauphin - Shelburne VT, US
Mark Masters - Essex Junction VT, US
Judith H. McCullen - Essex Junction VT, US
Sarah C. Braasch - Richmond VT, US
Michael H. Sitko - Jericho VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716 4, 716 5
Abstract:

The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

Methodology For Improving Device Performance Prediction From Effects Of Active Area Corner Rounding
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US Patent:

7818693, Oct 19, 2010
Filed:

Jan 8, 2008
Appl. No.:

11/971015
Inventors:

Dureseti Chidambarrao - Weston CT, US
Gerald M. Davidson - Essex Junction VT, US
Paul A. Hyde - Essex Junction VT, US
Judith H. McCullen - Essex Junction VT, US
Shreesh Narasimha - Beacon NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
G06F 9/45
G06G 7/48
US Classification:

716 2, 716 4, 716 5, 716 8, 716 19, 703 4, 703 13, 703 15
Abstract:

A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.

Compact Model Methodology For Pc Landing Pad Lithographic Rounding Impact On Device Performance
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US Patent:

7979815, Jul 12, 2011
Filed:

Jan 8, 2008
Appl. No.:

11/970990
Inventors:

Dureseti Chidambarrao - Weston CT, US
Gerald M. Davidson - Essex Junction VT, US
Paul A. Hyde - Essex Junction VT, US
Judith H. McCullen - Essex Junction VT, US
Shreesh Narasimha - Beacon NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
G06F 9/45
US Classification:

716101, 716 50, 716100, 716106, 716108, 716111, 716112, 716113, 716132, 716136, 703 4, 703 13, 703 15
Abstract:

A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Methodology For Improving Device Performance Prediction From Effects Of Active Area Corner Rounding
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US Patent:

8296691, Oct 23, 2012
Filed:

Jan 8, 2008
Appl. No.:

11/971015
Inventors:

Dureseti Chidambarrao - Weston CT, US
Gerald M. Davidson - Essex Junction VT, US
Paul A. Hyde - Essex Junction VT, US
Judith H. McCullen - Essex Junction VT, US
Shreesh Narasimha - Beacon NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
G06F 9/45
G06G 7/48
US Classification:

716101, 716 50, 716100, 716104, 716106, 716132, 703 4, 703 13, 703 15
Abstract:

A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.