Judson R Holt from 8 North Rdg, Burnt Hills, NY 12019, age 50

Resumes

Judson Holt

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Judson Holt

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Location:

United States

Us Patents

Ultra-Thin Body Super-Steep Retrograde Well (Ssrw) Fet Devices
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US Patent:

7002214, Feb 21, 2006
Filed:

Jul 30, 2004
Appl. No.:

10/710736
Inventors:

Diane C. Boyd - LaGrangeville NY, US
Judson R. Holt - Wappingers Falls NY, US
MeiKei Ieong - Wappingers Falls NY, US
Renee T. Mo - White Plains NY, US
Zhibin Ren - Hopewell Junction NY, US
Ghavam G. Shahidi - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 27/12
US Classification:

257351, 257347, 438153, 438154
Abstract:

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e. g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

Chemical Treatment To Retard Diffusion In A Semiconductor Overlayer
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US Patent:

7071103, Jul 4, 2006
Filed:

Jul 30, 2004
Appl. No.:

10/710737
Inventors:

Kevin K. Chan - Staten Island NY, US
Huajie Chen - Danbury CT, US
Michael A. Gribelyuk - Stamford CT, US
Judson R. Holt - Wappingers Falls NY, US
Woo-Hyeong Lee - Poughquag NY, US
Ryan M. Mitchell - Wake Forest NC, US
Renee T. Mo - White Plains NY, US
Dan M. Mocuta - Lagrangeville NY, US
Werner A. Rausch - Stormville NY, US
Paul A. Ronsheim - Hopewell Junction NY, US
Henry K. Utomo - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/44
US Classification:

438653, 438627, 438643
Abstract:

The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

Pre-Epitaxial Disposable Spacer Integration Scheme With Very Low Temperature Selective Epitaxy For Enhanced Device Performance
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US Patent:

7381623, Jun 3, 2008
Filed:

Jan 17, 2007
Appl. No.:

11/623882
Inventors:

Huajie Chen - Danbury CT, US
Judson R. Holt - Wappingers Falls NY, US
Kern Rim - Yorktown Heights NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/8234
H01L 21/336
H01L 21/331
H01L 21/36
US Classification:

438300, 438303, 438305, 438230, 438151, 438197, 438595, 438607, 438478, 438357, 257E21431, 257E2143, 257E21634, 257E2164
Abstract:

The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

Metal Oxide Field Effect Transistor With A Sharp Halo And A Method Of Forming The Transistor
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US Patent:

7384835, Jun 10, 2008
Filed:

May 25, 2006
Appl. No.:

11/420318
Inventors:

Huajie Chen - Danbury CT, US
Judson R Holt - Wappingers Falls NY, US
Rangarajan Jagannathan - Hopewell Junction NY, US
Wesley C Natzle - New Paltz NY, US
Michael R Sievers - Poughkeepsie NY, US
Richard S Wise - Newburgh NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/335
US Classification:

438197, 257E21435
Abstract:

Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

High Performance Field Effect Transistors On Soi Substrate With Stress-Inducing Material As Buried Insulator And Methods
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US Patent:

7388278, Jun 17, 2008
Filed:

Mar 24, 2005
Appl. No.:

11/088595
Inventors:

Judson R. Holt - Wappingers Falls NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 29/06
US Classification:

257627, 257632, 257649, 257E29108
Abstract:

The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

Stressed Field Effect Transistors On Hybrid Orientation Substrate
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US Patent:

7405436, Jul 29, 2008
Filed:

Jan 5, 2005
Appl. No.:

11/029797
Inventors:

Dureseti Chidambarrao - Weston CT, US
Judson R. Holt - Wappingers Falls NY, US
Meikei Ieong - Wappingers Falls NY, US
Siddhartha Panda - Beacon NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 29/04
H01L 21/8238
US Classification:

257204, 257627, 257E27108, 257E21632, 438199
Abstract:

A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon
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US Patent:

7473594, Jan 6, 2009
Filed:

Jul 25, 2006
Appl. No.:

11/459730
Inventors:

Ashima B. Chakravarti - Hopewell Junction NY, US
Dureseti Chidambarrao - Weston CT, US
Judson R. Holt - Wappingers Falls NY, US
Yaocheng Liu - Elmsford NY, US
Kern Rim - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/8238
US Classification:

438199, 257E2913
Abstract:

An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

Hybrid Orientation Substrate And Method For Fabrication Of Thereof
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US Patent:

7482209, Jan 27, 2009
Filed:

Nov 13, 2006
Appl. No.:

11/559151
Inventors:

Haining S. Yang - Wappingers Falls NY, US
Henry K. Utomo - Newburgh NY, US
Judson R. Holt - Wappingers Falls NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/84
US Classification:

438150, 257E21561
Abstract:

A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.