Judy D Hoyt

US Patent:

7867859, Jan 11, 2011

Filed:

Jun 17, 2008

Appl. No.:

12/140955

Inventors:

Steven Hung - San Francisco CA, US
Judy L. Hoyt - Belmont MA, US
James F. Gibbons - Palo Alto CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

H01L 21/336
H01L 21/20
H01L 21/4763
H01L 21/3205

US Classification:

438283, 438284, 438303, 438584, 438586, 438592

Abstract:

Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive.

US Patent:

20040113211, Jun 17, 2004

Filed:

Jan 16, 2004

Appl. No.:

10/450476

Inventors:

Steven Hung - San Francisco CA, US
Judy Hoyt - Belmont MA, US
James Gibbons - Palo Alto CA, US

International Classification:

H01L029/76

US Classification:

257/407000

Abstract:

Semiconductor device () performance is improved via a gate structure () having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment of the present invention, the design threshold voltage of a semiconductor device () is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device () at a selected voltage. The gate is formed having two different conductive materials () with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive material is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device (). In addition, by selecting the order of the layers, carrier depletion in the gate electrode can be avoided. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices, including any modem MOS transistor, providing independent adjustment of the channel doping, semiconductor alloy composition, and the threshold voltage of the device, thus enabling improved performance. The ability to reduce gate depletion effects also provides enhanced device current drive.

US Patent:

50844113, Jan 28, 1992

Filed:

Nov 29, 1988

Appl. No.:

7/277593

Inventors:

Stephen Laderman - Menlo Park CA
Martin Scott - San Francisco CA
Theodore I. Kamins - Palo Alto CA
Judy L. Hoyt - Palo Alto CA
Clifford A. King - Palo Alto CA
James F. Gibbons - Palo Alto CA
David B. Noble - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2120

US Classification:

437131

Abstract:

Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si. sub. 1-x Ge. sub. x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625. degree. to 1000. degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625. degree. and 825. degree. C.

US Patent:

52565505, Oct 26, 1993

Filed:

Jun 12, 1991

Appl. No.:

7/715054

Inventors:

Stephen Laderman - Menlo Park CA
Martin Scott - San Francisco CA
Theodore I. Kamins - Palo Alto CA
Judy L. Hoyt - Palo Alto CA
Clifford A. King - Palo Alto CA
James F. Gibbons - Palo Alto CA
David B. Noble - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 21205

US Classification:

437106

Abstract:

The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer. The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth.

US Patent:

52022846, Apr 13, 1993

Filed:

Dec 1, 1989

Appl. No.:

7/444464

Inventors:

Theodore I. Kamins - Palo Alto CA
David B. Noble - Sunnyvale CA
Judy L. Hoyt - Palo Alto CA
James F. Gibbons - Palo Alto CA
Martin P. Scott - San Francisco CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2120
H01L 21205

US Classification:

437 89

Abstract:

Several methods are disclosed for minimizing the number of defects or misfit locations in a SiGe layer selectively or non-selectively deposited on a partially oxide masked Si substrate.

US Patent:

47875518, Nov 29, 1988

Filed:

May 4, 1987

Appl. No.:

7/046848

Inventors:

Judy L. Hoyt - Palo Alto CA
Kenneth E. Williams - Los Altos CA
James F. Gibbons - Palo Alto CA

Assignee:

Stanford University - Stanford CA

International Classification:

B23K 3102

US Classification:

228179

Abstract:

Disclosed is a method of welding a temperature-sensing thermocouple to a silicon wafer for sensing the temperature of the wafer during rapid thermal processing using TIG welding and/or electron-beam welding. In one embodiment, a ball of silicon is formed on the bead at one end of a thermocouple by placing the thermocouple on a silicon chip and then melting the silicon chip with a TIG welder. The ball and thermocouple are then placed on the surface of a silicon wafer and the ball and surface are then melted whereby the ball of silicon flows into the silicon wafer. In placing the thermocouple on an edge portion of a silicon wafer, the wafer is supported on a tantalum plate with the edge portion of the wafer extending beyond the plate. A molybdenum sheet is positioned on the top surface of the wafer with the edge portion of the wafer exposed. A TIG arc is established with the molybdenum layer and then the arc is moved to the edge portion of the wafer for melting the silicon.