Judy A Teske from 13256 Owatonna Ct NE, Minneapolis, MN 55449, age 78, Phone: 6127201458

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Location:

Minneapolis, MN

Industry:

Government Administration

Work:

State of MN
Workforce Development Specialist 3

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Clock Monitor For Use With Vlsi Chips
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US Patent:

48602884, Aug 22, 1989
Filed:

Oct 23, 1987
Appl. No.:

7/112916
Inventors:

Judy L. Teske - Burnsville MN
Brian D. Borchers - Burnsville MN
Don A. Daane - Burnsville MN
Daniel J. Baxter - St. Paul MN
William G. Ehrich - Minneapolis MN
Assignee:

Control Data Corporation - Minneapolis MN
International Classification:

H04L 700
US Classification:

371 1
Abstract:

This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

Flexible Vlsi On-Chip Maintenance And Test System With Unit I/O Cell Design
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US Patent:

49127098, Mar 27, 1990
Filed:

Oct 23, 1987
Appl. No.:

7/112920
Inventors:

Judy L. Teske - Burnsville MN
Daniel J. Baxter - St. Paul MN
Don A. Daane - Burnsville MN
Brian D. Borchers - Burnsville MN
David H. Allen - Eagan MN
Michael F. Maas - Maplewood MN
Assignee:

Control Data Corporation - Minneapolis MN
International Classification:

G01R 3128
US Classification:

371 221
Abstract:

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.