Judy Lynn Teske from Chapel Hill, NC, age 65

Vehicle Records

Judy Teske
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Address:

1714 Moccasin Ct, Henderson, NV 89014
VIN:

JHLRE48727C083489
Make:

HONDA
Model:

CR-V
Year:

2007

Resumes

Jubilada

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Location:

Henderson, NV

Industry:

Biotechnology

Work:

Jubilada
Diamond Resorts International
Technical Project Manager
Experis It Feb 2013 - Sep 2015
Project Management Consultant
Scitech Hookup Jun 2012 - Aug 2015
Co-Organizer
Parallel Innovation Labs Dec 2012 - Aug 2015
Director -- Board of Directors

Education:

University of St. Thomas 1995 - 1997
Master of Business Administration, Masters North Dakota State University 1978 - 1982
Minot High School

Skills:

Project Management
Product Management
Product Development
Program Management
Argentine Tango
Networking
Team Leadership
Process Improvement
Manufacturing
Start Ups
Software Project Management
International Marketing
Regulations
Strategic Planning
Quality Assurance
Analysis
Cross Functional Team Leadership
Engineering
Training
Strategy
Leadership
Change Management
Forecasting
Budgets
Sdlc
Testing
Marketing Strategy
Project Planning
Competitive Analysis
Product Marketing
Software Documentation
Business Process
Entrepreneurship
Risk Management
Management
Contract Negotiation
Market Research
Vendor Management
Marketing
Business Intelligence
Business Analysis
Itil
Ms Project
Pmp
Visio
Crm
Business Process Improvement
Agile Methodologies
Team Building
Software Development

Languages:

English
Spanish
French

Judy Teske

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Us Patents

Clock Monitor For Use With Vlsi Chips
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US Patent:

48602884, Aug 22, 1989
Filed:

Oct 23, 1987
Appl. No.:

7/112916
Inventors:

Judy L. Teske - Burnsville MN
Brian D. Borchers - Burnsville MN
Don A. Daane - Burnsville MN
Daniel J. Baxter - St. Paul MN
William G. Ehrich - Minneapolis MN
Assignee:

Control Data Corporation - Minneapolis MN
International Classification:

H04L 700
US Classification:

371 1
Abstract:

This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

Flexible Vlsi On-Chip Maintenance And Test System With Unit I/O Cell Design
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US Patent:

49127098, Mar 27, 1990
Filed:

Oct 23, 1987
Appl. No.:

7/112920
Inventors:

Judy L. Teske - Burnsville MN
Daniel J. Baxter - St. Paul MN
Don A. Daane - Burnsville MN
Brian D. Borchers - Burnsville MN
David H. Allen - Eagan MN
Michael F. Maas - Maplewood MN
Assignee:

Control Data Corporation - Minneapolis MN
International Classification:

G01R 3128
US Classification:

371 221
Abstract:

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.