Julia K. Cline - Mountain View CA, US Eugene C. Ho - Saratoga CA, US Bret G. Stott - Los Altos Hills CA, US Frederick A. Ware - Los Altos Hills CA, US
Assignee:
RAMBUS INC. - Los Altos CA
International Classification:
G06F 12/00 G06F 1/04
US Classification:
711105, 711167, 713600, 711E12001
Abstract:
Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.
Multi-Element Memory Device With Power Control For Individual Elements
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
Multi-Element Memory Device With Power Control For Individual Elements
- Sunnyvale CA, US Julia Kelly Cline - San Francisco CA, US Wayne Frederick Ellis - Saratoga CA, US
International Classification:
G06F 1/28 G06F 13/42 G06F 1/32 G11C 5/06
Abstract:
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
Multi-Element Memory Device With Power Control For Individual Elements
- Sunnyvale CA, US Julia Kelly Cline - San Francisco CA, US Wayne Frederick Ellis - Saratoga CA, US
International Classification:
G06F 1/28 G06F 13/42 G06F 1/32
Abstract:
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
Multi-Element Memory Device With Power Control For Individual Elements
Deborah Lindsey Dressler - Newark CA, US Julia Kelly Cline - San Francisco CA, US Wayne Frederick Ellis - Saratoga CA, US
Assignee:
RAMBUS INC. - Sunnyvale CA
International Classification:
G06F 1/32
US Classification:
713324
Abstract:
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes side-band circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
Rambus since Feb 2012
Manager, System Engineering Team
Rambus Jan 2011 - Feb 2012
Manager, System Technology Team
Rambus Sep 2009 - Jan 2011
Senior Member of Technical Staff: Production Engineering
Rambus Jan 2007 - Sep 2009
Sr. Member of Technical Staff: Digital Circuit Design
Rambus Dec 2005 - Jan 2007
Member of Technical Staff: Circuit Designer
Education:
Massachusetts Institute of Technology 2002 - 2004
MSc, Circuit Design
Brown University 1998 - 2002
ScB, Electrical Engineering
o we do it? And what does the vehicle look like if we do that? I think its going to expand what we think of when it comes to nuclear propulsion, said Julia Cline, a mentor for the project in NASA Langleys Research Directorate, who led the centers participation in the Nuclear Electric Propulsion
Date: Jan 10, 2025
Category: Science
Source: Google
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James James Hill (1970-1974), Julie Bixby (1969-1973), Donna Grim (1976-1980), Jim Joyner (1969-1973), Julia Cline (1969-1973), Debbie Seahorn (1970-1974)