Julia D Harper

US Patent:

7774642, Aug 10, 2010

Filed:

Feb 17, 2005

Appl. No.:

11/061236

Inventors:

Bjørn Dag Johnsen - Oslo, NO
David M. Brean - Boston MA, US
Srinivas Madhur - Westford MA, US
Julia D. Harper - Arlington MA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 11/00

US Classification:

714 6, 714 4, 714 5, 714 40, 714 41, 714 44, 714 47

Abstract:

A fault zone definition mechanism groups components of an interconnect environment having a common point of dependence into a logical group defining a fault zone for the interconnect environment. The fault zone definition mechanism may be implemented in software, firmware or hardware, or a combination of two or more of software, firmware and hardware. A method for defining a fault zone is also disclosed.

US Patent:

20020129115, Sep 12, 2002

Filed:

Mar 7, 2001

Appl. No.:

09/801474

Inventors:

Lisa Noordergraaf - Chelmsford MA, US
Julia Harper - Arlington MA, US
Prakash Khemani - Karnataka, IN

International Classification:

G06F015/167

US Classification:

709/213000

Abstract:

A distributed shared memory multiprocessor computer system utilizes page placement policies to reduce data access latencies. Pages of memory are allocated to nodes in a distributed shared memory multiprocessor computer system. A placement policy database is maintained which indicates a placement policy for each page in the system. Upon an access to a page, the placement policy corresponding to the accessed page is determined and the indicated policy is acted upon. A Migrate on Next Touch policy provides that the next access to a page with this policy will cause the page to migrate to the node of the accessing CPU. A Memory Follows Lightweight Process (LWP) policy ensures that pages within a given address range are always local to a specified LWP. A Migrate on Every Touch policy provides that pages within a given address range are migrated to an accessing CPU on every touch. A Replicate on Remote Touch policy provides for replication of a page in the memory of each accessing CPU's domain. Finally, a Replicate on All policy provides that upon an access to a given page, that page is replicated on all nodes in the system.

US Patent:

20130290752, Oct 31, 2013

Filed:

Apr 30, 2012

Appl. No.:

13/460696

Inventors:

Blake A. Jones - Oakland CA, US
Julia D. Harper - Arlington MA, US
Jonathan William Adams - San Francisco CA, US

Assignee:

ORACLE INTERNATIONAL CORPORATION - Redwood Shores CA

International Classification:

G06F 1/32
G06F 12/10

US Classification:

713320, 711206, 711E12059

Abstract:

A system including memory and a resource controller. The memory includes a first memgroup and a second memgroup, wherein the first memgroup comprises a first physical page mapped to a virtual page, and wherein the second memgroup comprises a second physical page. The resource controller is configured to receive a request to stop the first memgroup, instruct a memory power management subsystem to mark the first memgroup as stopped in response to receiving the request to stop the first memgroup, wherein no free pages are allocated from the first memgroup after the first memgroup is marked as stopped, remap the virtual page to the second physical page in response to the marking the first memgroup as stopped, and reduce power to the first memgroup in response to a determination that the first physical page is not mapped to the virtual page.

US Patent:

20190079795, Mar 14, 2019

Filed:

Sep 8, 2017

Appl. No.:

15/699027

Inventors:

- Redwood City CA, US
Milton Shih - Westford MA, US
Matthew Cohen - Cambridge MA, US
Kenneth Chan - Saratoga CA, US
Ramaswamy Sivaramakrishnan - San Jose CA, US
Julia Harper - Arlington MA, US
Peter Dunlap - Boulder CO, US

International Classification:

G06F 9/48
G06F 13/42
G06F 11/07
G06F 21/60

Abstract:

A method and system for processing data are disclosed. A processor, in response to executing a software program, may write an entry in a work queue. The entry may include an operation, and a location of data stored in an input buffer, and a location in an output buffer to write processed data. The processor may also generate a notification that at least one entry in the work queue is ready to be processed. The data transformation unit may assign the entry to a data transformation circuit, and retrieve the data from the input buffer using the location. The data transformation unit may also perform to the operation on the retrieved data to generate updated data, generate a completion message in response to completion of the operation, and store the updated data in an output buffer. An interface unit may relay transactions between the processor and the data transformation unit.

US Patent:

20170286354, Oct 5, 2017

Filed:

Jun 21, 2017

Appl. No.:

15/629293

Inventors:

- Redwood City CA, US
Matthew Cohen - Cambridge MA, US
Rahoul Puri - Los Altos CA, US
Tayfun Kocaoglu - Los Gatos CA, US
John Johnson - San Jose CA, US
David Kahn - Makawao HI, US
Alan Adamson - San Diego CA, US
Sriram Jayakumar - Lexington MA, US
Julia Harper - Arlington MA, US
Robert G. Sheldon - Duxbury MA, US
Mark Kanda - Austin TX, US

International Classification:

G06F 13/42
G06F 9/455
G06F 13/36

Abstract:

An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.

US Patent:

20170139721, May 18, 2017

Filed:

Nov 18, 2015

Appl. No.:

14/944893

Inventors:

- Redwood City CA, US
Sriram Jayakumar - Lexington MA, US
Rahoul Puri - Los Altos CA, US
Matthew Cohen - Cambridge MA, US
Julia Harper - Arlington MA, US
Alan Adamson - San Diego CA, US
John Johnson - San Jose CA, US

International Classification:

G06F 9/44
G06F 13/20

Abstract:

An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.

US Patent:

20170139873, May 18, 2017

Filed:

Nov 18, 2015

Appl. No.:

14/944835

Inventors:

- Redwood City CA, US
Matthew Cohen - Cambridge MA, US
Rahoul Puri - Los Altos CA, US
John Johnson - San Jose CA, US
Alan Adamson - San Diego CA, US
Julia Harper - Arlington MA, US

International Classification:

G06F 13/42
G06F 13/10
G06F 9/455
G06F 13/40

Abstract:

An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

US Patent:

20150006918, Jan 1, 2015

Filed:

Jul 1, 2013

Appl. No.:

13/932715

Inventors:

- Redwood Shores CA, US
Julia Diane Harper - Arlington MA, US

International Classification:

G06F 1/26
G06F 9/455

US Classification:

713300

Abstract:

A method for obtaining power management data for a system executing by at least one processor, where a plurality of logical domains are executing on the system. The method includes determining, using the power management data, power consumption for each of the plurality of logical domains and receiving a request for power consumption information for the system. The method further includes providing, in response to the request, the power consumption information, where the power consumption information specifies the power consumption for at least one of the plurality of logical domains.