Julia C Perez

US Patent:

7581202, Aug 25, 2009

Filed:

May 31, 2007

Appl. No.:

11/756187

Inventors:

Julia Perez - Tempe AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 8, 716 4

Abstract:

A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad array layout of the at least one pad array as a function of a set of keywords. The control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords. The keywords each define at least (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array. The pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.

US Patent:

20060288315, Dec 21, 2006

Filed:

Jun 20, 2005

Appl. No.:

11/157025

Inventors:

Julia Perez - Tempe AZ, US
Leo Kasel - Mesa AZ, US

International Classification:

G06F 17/50

US Classification:

716003000

Abstract:

A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation () on a structure layout. The compiling interpretation () includes i) determining and analyzing shape relationships of the structure layout (), and ii) mapping shapes and calculating properties of mapped shapes (). The method also includes generating code () in response to the compiling interpretation, wherein the generated code is representative of one or more parameterized cells.

US Patent:

20170169156, Jun 15, 2017

Filed:

Dec 14, 2015

Appl. No.:

14/967626

Inventors:

- Austin TX, US
Julia Perez - Tempe AZ, US

International Classification:

G06F 17/50

Abstract:

A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. The schematic design tool computes layout structure data based on the temporary layout and provides the layout structure data to a place and route tool within the design tool system that, in turn, generates a layout based on the layout structure data The design tool system then generates mask layer data based upon the layout that is configured to generate masks for construction of an integrated circuit corresponding to the analog circuit schematic.