Julian A Sanchez

US Patent:

62810626, Aug 28, 2001

Filed:

Jun 16, 1998

Appl. No.:

9/098078

Inventors:

Julian J. Sanchez - Mesa AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218238
H01L 21336
H01L 2976

US Classification:

438217

Abstract:

A novel high-speed, highly reliable VSLI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.

US Patent:

55830676, Dec 10, 1996

Filed:

Feb 16, 1996

Appl. No.:

8/603151

Inventors:

Julian J. Sanchez - Mesa AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 44

Abstract:

A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member. A second source and second drain region of the second conductivity type are formed in the first source and first drain regions, respectively.

US Patent:

60810106, Jun 27, 2000

Filed:

Feb 28, 1994

Appl. No.:

8/203685

Inventors:

Julian J. Sanchez - Mesa AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976
H01L 2994
H01L 31062

US Classification:

257345

Abstract:

A novel high-speed, highly reliable VLSI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.

Address:

8006 Keller St, Houston, TX 77012

VIN:

1GNFC13J77R199699

Make:

CHEVROLET

Model:

TAHOE

Year:

2007