Jun Zhou from 4743 Lakeside Meadow Dr, Missouri City, TX 77459, age 43

Us Patents

Hybrid Linear Wire Model Approach To Tuning Transistor Widths Of Circuits With Rc Interconnect
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US Patent:

7325210, Jan 29, 2008
Filed:

Mar 10, 2005
Appl. No.:

11/077043
Inventors:

Vasant Rao - Fishkill NY, US
Cindy Washburn - Poughquag NY, US
Jun Zhou - Austin TX, US
Jeffrey P. Soreff - Poughkeepsie NY, US
Patrick M. Williams - Salt Point NY, US
David J. Hathaway - Underhill VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716 6, 716 2, 703 16
Abstract:

A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.

Accurate Parasitics Estimation For Hierarchical Customized Vlsi Design
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US Patent:

7913216, Mar 22, 2011
Filed:

Feb 16, 2008
Appl. No.:

12/032643
Inventors:

Ronald Dennis Rose - Essex Junction VT, US
Jun Zhou - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716119, 716125, 716126
Abstract:

Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

System And Method For Improved Placement In Custom Vlsi Circuit Design With Schematic-Driven Placement
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US Patent:

8028265, Sep 27, 2011
Filed:

Jul 31, 2008
Appl. No.:

12/183898
Inventors:

William D. Ramsour - Pflugerville TX, US
Samuel I. Ward - Austin TX, US
Jun Zhou - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
G06F 15/04
US Classification:

716122, 716118, 716119, 716139
Abstract:

A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates.