June Swanson Cline

US Patent:

7115210, Oct 3, 2006

Filed:

Feb 2, 2004

Appl. No.:

10/708009

Inventors:

Robert A. Calderoni - Fairfield VT, US
June Cline - South Burlington VT, US
Kellie L. Dutra - Essex Junction VT, US
Ronald G. Meunier - Essex Junction VT, US
Joseph P. Walko - Jericho VT, US
Justin Wai-chow Wong - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01I 21/302

US Classification:

216 59, 216 61, 118712, 275E21528, 438 14, 438 16, 455118

Abstract:

Disclosed is a method and system for detecting abnormal plasma discharge that is useful in, for example, detecting plasma leakage in a reactive ion etching (RIE) chamber. The system includes electrical contacts connected to the chamber that provide an input signal to the chamber. This input signal can be generated by a radio frequency (RF) generator that is connected to the electrical contacts. A variable power controller connected to the RF generator gradually increases (ramps) the power of the input signal being supplied to the chamber.

US Patent:

7573085, Aug 11, 2009

Filed:

Jul 20, 2006

Appl. No.:

11/458828

Inventors:

June Cline - South Burlington VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Colchester VT, US
Jeffrey C. Maling - Grand Isle VT, US
Lisa Y. Ninomiya - Ridgefield CT, US
Bruce W. Porth - Jericho VT, US
Steven M. Shank - Jericho VT, US
Jessica A. Trapasso - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/108

US Classification:

257296, 438736, 438739, 257E21035, 257E21023

Abstract:

A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

US Patent:

7893479, Feb 22, 2011

Filed:

Aug 10, 2009

Appl. No.:

12/538193

Inventors:

June Cline - Essex Junction VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Essex Junction VT, US
Jeffrey C. Maling - Essex Junction VT, US
Lisa Y. Ninomiya - Essex Junction VT, US
Bruce W. Porth - Essex Junction VT, US
Steven M. Shank - Essex Junction VT, US
Jessica A. Trapasso - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/108

US Classification:

257296, 257E21035, 257E21023, 438736

Abstract:

A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

US Patent:

20060081556, Apr 20, 2006

Filed:

Oct 15, 2004

Appl. No.:

10/711953

Inventors:

June Cline - South Burlington VT, US
Dinh Dang - Essex Junction VT, US
Mark Lagerquist - Colchester VT, US
Jeffrey Maling - Grand Isle VT, US
Lisa Ninomiya - Ridgefield CT, US
Bruce Porth - Jericho VT, US
Steven Shank - Jericho VT, US
Jessica Trapasso - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01B 13/00
B44C 1/22

US Classification:

216017000, 216041000, 216059000

Abstract:

A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.