Jung-Hui H Lin

US Patent:

55894232, Dec 31, 1996

Filed:

Oct 3, 1994

Appl. No.:

8/317045

Inventors:

Ted R. White - Austin TX
Bradley M. Somero - Austin TX
Mark A. Chonko - Austin TX
Jung-Hui Lin - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2170
H01L 2700
H01L 21465
H01L 21306

US Classification:

437228

Abstract:

A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).

US Patent:

50616471, Oct 29, 1991

Filed:

Oct 12, 1990

Appl. No.:

7/597946

Inventors:

Scott S. Roth - Austin TX
Carlos A. Mazure - Austin TX
Kent J. Cooper - Austin TX
Wayne J. Ray - Austin TX
Michael P. Woo - Austin TX
Jung-Hui Lin - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

437 40

Abstract:

A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (. PHI. ) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate.

US Patent:

56518587, Jul 29, 1997

Filed:

Jul 26, 1996

Appl. No.:

8/690192

Inventors:

Jung-Hui Lin - Gilbert AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 21306

US Classification:

1566461

Abstract:

A method for forming a tapered opening in a silicon substrate uses NF. sub. 3 and HBr. The NF. sub. 3 /HBr plasma etch allows both a good taper profile, 85. degree. to 60. degree. , as well as a good etch rate, approximately 2500 to 3000. ANG. /minute. Although not limited to a particular trench size, the present method is well suited for forming openings smaller than 0. 45. mu. m.

US Patent:

52104354, May 11, 1993

Filed:

Aug 16, 1991

Appl. No.:

7/745652

Inventors:

Scott S. Roth - Austin TX
Carlos A. Mazure - Austin TX
Kent J. Cooper - Austin TX
Wayne J. Ray - Austin TX
Michael P. Woo - Austin TX
Jung-Hui Lin - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2976
H01L 2994
H01L 31062

US Classification:

257344

Abstract:

A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (. PHI. ) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate.

US Patent:

55389228, Jul 23, 1996

Filed:

Jan 25, 1995

Appl. No.:

8/378990

Inventors:

Kent J. Cooper - Austin TX
Jung-Hui Lin - Austin TX
Scott S. Roth - Austin TX
Bernard J. Roman - Austin TX
Carlos A. Mazure - Austin TX
Wayne J. Ray - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2146

US Classification:

437195

Abstract:

A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

US Patent:

52197930, Jun 15, 1993

Filed:

Jun 3, 1991

Appl. No.:

7/709554

Inventors:

Kent J. Cooper - Austin TX
Jung-Hui Lin - Austin TX
Scott S. Roth - Austin TX
Bernard J. Roman - Austin TX
Carlos A. Mazure - Austin TX
Wayne J. Ray - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2146

US Classification:

437195

Abstract:

A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.