Junxiong D Deng

US Patent:

7729672, Jun 1, 2010

Filed:

Mar 8, 2007

Appl. No.:

11/683913

Inventors:

Junxiong Deng - San Diego CA, US
Prasad Gudem - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H04B 1/04
H04M 1/00

US Classification:

4551271, 4555521, 330136

Abstract:

An RF output power amplifier (PA) of a cellular telephone includes first and second Class AB amplifier circuits. If the cellular telephone is to operate in a high power operating mode, then the first amplifier drives the PA output terminal. The power transistor(s) in the first amplifier is/are biased at a first DC current and a first DC voltage so as to optimize efficiency and linearity at high output powers. If the cellular telephone is to operate in a low power operating mode, then the second amplifier drives the output terminal. The power transistor(s) in the second amplifier is/are biased at a second DC current and a second DC voltage so as to optimize efficiency and linearity at low output powers. By sizing the power transistors in the amplifiers appropriately, emitter current densities are maintained substantially equal so that PA power gain is the same in the two operating modes.

US Patent:

7746169, Jun 29, 2010

Filed:

Feb 6, 2008

Appl. No.:

12/027107

Inventors:

Junxiong Deng - San Diego CA, US
Christian Holenstein - San Diego CA, US
Namsoo Kim - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03F 3/45

US Classification:

330254, 330253

Abstract:

A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.

US Patent:

7899426, Mar 1, 2011

Filed:

Nov 7, 2007

Appl. No.:

11/936305

Inventors:

Aleksandar Tasic - San Diego CA, US
Junxiong Deng - San Diego CA, US
Namsoo Kim - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04B 7/00
H04B 1/16

US Classification:

455286, 455334, 4555501

Abstract:

In a SAW-less receiver involving a passive mixer, novel degenerative impedance elements having substantial impedances are disposed in incoming signal paths between the differential signal output leads of a low-noise amplifier (LNA) and the differential signal input leads of the passive mixer. The passive mixer outputs signals to a transimpedance amplifier and baseband filter (TIA). Providing the novel degenerative impedance elements decreases noise in the overall receiver as output from the TIA, with only minimal degradation of other receiver performance characteristics. In some examples, the passive mixer receives local oscillator signals having duty cycles of substantially less than fifty percent. In some examples, the degenerative impedance elements can have one of several impedances.

US Patent:

7936217, May 3, 2011

Filed:

Nov 29, 2007

Appl. No.:

11/947570

Inventors:

Junxiong Deng - San Diego CA, US
Gurkanwal Singh Sahota - San Diego CA, US
Solti Peng - Plano TX, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03F 3/18

US Classification:

330264, 330267

Abstract:

A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

US Patent:

8095082, Jan 10, 2012

Filed:

Oct 10, 2007

Appl. No.:

11/870365

Inventors:

Junxiong Deng - San Diego CA, US
Maulin Pareshbhai Bhagat - San Diego CA, US
Gurkanwal Singh Sahota - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H04B 1/02
H04B 1/04
H01Q 11/12

US Classification:

455 91, 455118, 455124, 4551274

Abstract:

A transmitter includes a transformer and a transformer tuning circuit. The transformer transforms a differential radio frequency (RF) signal to a single-ended RF signal. The transformer tuning circuit tunes the transformer to permit the transmitter to transmit the single-ended RF signal in a first frequency band (e. g. , cellular frequency band) or a second frequency band (e. g. , PCS frequency band).

US Patent:

8102213, Jan 24, 2012

Filed:

Sep 23, 2009

Appl. No.:

12/565526

Inventors:

Aleksandar Tasic - San Diego CA, US
Junxiong Deng - San Diego CA, US
Zhang Jin - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03G 3/12

US Classification:

330283, 330311, 330295

Abstract:

A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.

US Patent:

8351978, Jan 8, 2013

Filed:

Aug 1, 2008

Appl. No.:

12/184608

Inventors:

Aleksandar Tasic - San Diego CA, US
Christian Holenstein - San Diego CA, US
Junxiong Deng - San Diego CA, US

International Classification:

H04M 1/00

US Classification:

4555501, 4552341, 4552481

Abstract:

A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

US Patent:

8368434, Feb 5, 2013

Filed:

Jul 15, 2010

Appl. No.:

12/836774

Inventors:

Aleksandar M. Tasic - San Diego CA, US
Junxiong Deng - San Diego CA, US
Dongjiang Qiao - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H03K 21/00

US Classification:

327115, 327117, 377 47

Abstract:

A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.