Kai C Chan

US Patent:

6677793, Jan 13, 2004

Filed:

Feb 3, 2003

Appl. No.:

10/357827

Inventors:

Kai Keung Chan - Fremont CA
Jung-Sheng Hoei - Newark CA
Pankaj Joshi - Milpitas CA
Leo Fang - Belmont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03L 706

US Classification:

327158, 327291

Abstract:

An automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.

US Patent:

8489971, Jul 16, 2013

Filed:

May 27, 2011

Appl. No.:

13/117955

Inventors:

Kai Keung Chan - Fremont CA, US
Kin Man Ng - Cupertino CA, US
Jason Bellorado - Santa Clara CA, US

Assignee:

SK hynix memory solutions inc. - San Jose CA

International Classification:

H03M 13/03

US Classification:

714795

Abstract:

A system for adapting coefficients of a soft output Viterbi algorithm (SOVA) is disclosed. The system includes a receiver configured to select an output of an SOVA detector at least in part based on a criterion. The receiver is configured to store the selected output of the SOVA detector. The receiver is further configured to store a signal that corresponds to the stored selected output of the SOVA detector, wherein the input to the SOVA detector is derived from the signal. The receiver is further configured to adapt a plurality of coefficients of the SOVA detector at least in part based on the stored selected output of the SOVA detector, the stored signal, and a corresponding data pattern. The system includes an interface coupled to the receiver and configured to receive samples.

US Patent:

8631311, Jan 14, 2014

Filed:

Apr 23, 2012

Appl. No.:

13/453729

Inventors:

Kai Keung Chan - Fremont CA, US
Yu Kou - San Jose CA, US
Wing Hui - San Jose CA, US

Assignee:

SK hynix memory solutions inc. - San Jose CA

International Classification:

G06F 11/00

US Classification:

714799, 714769

Abstract:

A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.

US Patent:

20180062654, Mar 1, 2018

Filed:

Feb 2, 2015

Appl. No.:

14/612076

Inventors:

Kai Keung Chan - Fremont CA, US
David Tsang - Los Altos CA, US
Chao-Chiang Chen - Cupertino CA, US

Assignee:

Agate Logic Inc. - Santa Clara CA

International Classification:

H03K 19/0175
H03K 19/02
H03K 19/177

Abstract:

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

US Patent:

20160301420, Oct 13, 2016

Filed:

Jun 15, 2016

Appl. No.:

15/183723

Inventors:

- Sunnyvale CA, US
Kai Keung Chan - Fremont CA, US
Yu Kou - San Jose CA, US

International Classification:

H03M 1/10
H03M 1/12
H03M 1/34

Abstract:

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

US Patent:

20160126970, May 5, 2016

Filed:

Oct 31, 2014

Appl. No.:

14/530224

Inventors:

- Sunnyvale CA, US
Kai Keung Chan - Fremont CA, US
Yu Kou - San Jose CA, US

International Classification:

H03M 1/10
H03M 1/36
H03M 1/12

Abstract:

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.