Kai C Cheng

US Patent:

6574219, Jun 3, 2003

Filed:

Aug 6, 1998

Appl. No.:

09/130399

Inventors:

Gilbert A. Neiger - Portland OR 97212
Nicholas D. Wade - Portland OR 97229
Kai Cheng - Portland OR 97229

International Classification:

H04J 326

US Classification:

370394, 370412

Abstract:

In some embodiments, a computer system includes nodes connected through conductors to form a ring. Messages are transmitted on the ring and at least some of the nodes each include control circuitry to receive the messages in a node reception order that is different for each node and order the messages in a global order that is the same for each node having the control circuitry.

US Patent:

6636962, Oct 21, 2003

Filed:

Dec 10, 1999

Appl. No.:

09/459743

Inventors:

Jiming Sun - Portland OR
Kai Cheng - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9445

US Classification:

713 1

Abstract:

A chipset in a computer system is initialized without intervention by the processor, thereby reducing the time required to boot the computer system. The system includes a nonvolatile storage device for storing configuration data for the chipset. Logic circuitry loads the configuration data into configuration registers in the chipset. The storage device and logic circuitry can be integrated into the chipset. A data pump can be used to load the configuration data into the configuration registers by serially pumping configuration data onto a scan line coupled to the configuration registers. In a system having more than one chipset, the chipsets can be initialized simultaneously to further reduce the amount of time required to boot the system. The configuration data can be downloaded into the storage device when the system is manufactured, or it can be downloaded from the processor the first time the system is powered up.

US Patent:

6810467, Oct 26, 2004

Filed:

Aug 21, 2000

Appl. No.:

09/643382

Inventors:

Manoj Khare - Saratoga CA
Faye A. Briggs - Portland OR
Kai Cheng - Portland OR
Lily Pao Looi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711146, 711144, 711145, 711140

Abstract:

An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the systems nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.

US Patent:

6857048, Feb 15, 2005

Filed:

Jan 17, 2002

Appl. No.:

10/046768

Inventors:

Linda J. Rankin - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711133, 711146, 711119, 711136

Abstract:

A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.

US Patent:

6912612, Jun 28, 2005

Filed:

Feb 5, 2003

Appl. No.:

10/358568

Inventors:

Suvansh K. Kapur - Portland OR, US
Kai Cheng - Portland OR, US
Robert J. Hoogland - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/36
G06F012/00
G01R031/08

US Classification:

710309, 710317, 370225, 370447, 711138, 711141

Abstract:

A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.

US Patent:

6915370, Jul 5, 2005

Filed:

Dec 20, 2001

Appl. No.:

10/029554

Inventors:

Linda J. Rankin - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/00

US Classification:

710305, 37039531

Abstract:

A multi-port switch is incorporated into a multi-node computer system and at least a first port of the multi-port switch is assigned to a first domain.

US Patent:

6959364, Oct 25, 2005

Filed:

Jun 28, 2002

Appl. No.:

10/186490

Inventors:

Robert J. Safranek - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711146, 711141

Abstract:

In some embodiments, the invention includes a snoop filter, wherein entries in the snoop filter are allocated in response to initial accesses of local cache lines by a remote node, but entries in the snoop filter are not allocated in response to accesses of the local cache lines by a local node. Other embodiments are described and claimed.

US Patent:

7058750, Jun 6, 2006

Filed:

May 10, 2000

Appl. No.:

09/569100

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.