Kaiwin W Lee

US Patent:

54834619, Jan 9, 1996

Filed:

Jun 10, 1993

Appl. No.:

8/074961

Inventors:

Kaiwin Lee - Sunnyvale CA
Lu Chung - Sunnyvale CA
Yuh-Zen Liao - Saratoga CA
Stephen Wuu - Sunnyvale CA

Assignee:

ARCSYS, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

364490

Abstract:

An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.