Kara B Tervooren
age ~49
from Frisco, TX
- Also known as:
-
- Kara R Tervooren
- Kara Renee Blackwood
- Kara R Blackwood
- Phone and address:
- 15036 Springwood Dr, Frisco, TX 75035
Kara Tervooren Phones & Addresses
- 15036 Springwood Dr, Frisco, TX 75035
- Richardson, TX
- Dallas, TX
- Plano, TX
- College Station, TX
- 4124 Binley Dr, Richardson, TX 75082
Work
-
Company:Fujitsu network communications (fnc)1999
-
Position:Asic verification engineer
Education
-
School / High School:Texas A&M University- College Station, TX1994
-
Specialities:B.S. in Electrical Engineering
Skills
Systemverilog • Asic • Specman • Fpga • Ethernet • Perl • Mixed Signal • Open Verification Methodology • Cadence • Pcie • Functional Verification • Simulations • Verilog • Uvm • Soc • Application Specific Integrated Circuits • Tcl • Dft • Vhdl • Leadership • Field Programmable Gate Arrays • Rtl Design • Modelsim • Ncsim • Ic • Vlsi • Altera • Hardware Architecture • Static Timing Analysis • Xilinx • Rtl Coding • Ovm • Universal Verification Methodology • Analog Circuits
Industries
Semiconductors
Resumes
Principal Member Technical Staff, Mixed Signal Verification At Maxim Integrated
view sourceLocation:
Dallas, TX
Industry:
Semiconductors
Work:
Maxim Integrated
Principal Member Technical Staff, Mixed Signal Verification at Maxim Integrated
Fujitsu Network Communications Sep 1999 - Dec 2012
Asic Verification Engineer
Cyrix Jun 1997 - Aug 1997
Perl Programmer
Mci Corporation Jun 1996 - Aug 1996
Labwindows and Cvi Programmer
Principal Member Technical Staff, Mixed Signal Verification at Maxim Integrated
Fujitsu Network Communications Sep 1999 - Dec 2012
Asic Verification Engineer
Cyrix Jun 1997 - Aug 1997
Perl Programmer
Mci Corporation Jun 1996 - Aug 1996
Labwindows and Cvi Programmer
Education:
Texas A&M University 1994 - 1999
Bachelors, Bachelor of Science, Electrical Engineering Plano Senior High School 1992 - 1994
Bachelors, Bachelor of Science, Electrical Engineering Plano Senior High School 1992 - 1994
Skills:
Systemverilog
Asic
Specman
Fpga
Ethernet
Perl
Mixed Signal
Open Verification Methodology
Cadence
Pcie
Functional Verification
Simulations
Verilog
Uvm
Soc
Application Specific Integrated Circuits
Tcl
Dft
Vhdl
Leadership
Field Programmable Gate Arrays
Rtl Design
Modelsim
Ncsim
Ic
Vlsi
Altera
Hardware Architecture
Static Timing Analysis
Xilinx
Rtl Coding
Ovm
Universal Verification Methodology
Analog Circuits
Asic
Specman
Fpga
Ethernet
Perl
Mixed Signal
Open Verification Methodology
Cadence
Pcie
Functional Verification
Simulations
Verilog
Uvm
Soc
Application Specific Integrated Circuits
Tcl
Dft
Vhdl
Leadership
Field Programmable Gate Arrays
Rtl Design
Modelsim
Ncsim
Ic
Vlsi
Altera
Hardware Architecture
Static Timing Analysis
Xilinx
Rtl Coding
Ovm
Universal Verification Methodology
Analog Circuits
Kara Blackwood Tervooren Richardson, TX
view sourceWork:
FUJITSU NETWORK COMMUNICATIONS (FNC)
1999 to 2000
ASIC Verification Engineer CYRIX SEMICONDUCTOR
Richardson, TX
1997 to 1997
PERL Programmer, Engineering Intern MCI Corporation
Richardson, TX
1996 to 1996
LabWindows/CVI Programmer, Engineering Intern
1999 to 2000
ASIC Verification Engineer CYRIX SEMICONDUCTOR
Richardson, TX
1997 to 1997
PERL Programmer, Engineering Intern MCI Corporation
Richardson, TX
1996 to 1996
LabWindows/CVI Programmer, Engineering Intern
Education:
Texas A&M University
College Station, TX
1994 to 1999
B.S. in Electrical Engineering
College Station, TX
1994 to 1999
B.S. in Electrical Engineering
Get Report for Kara B Tervooren from Frisco, TX, age ~49