Karan S Methe

from San Jose, CA

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Karan Methe Phones & Addresses

  • San Jose, CA

Work

  • Company:
    Sandisk corporation
    Jul 2012
  • Position:
    Asic design engineer ii

Education

  • School / High School:
    San Jose State University
    Aug 2010
  • Specialities:
    Master of Science in Electrical Engineering

Skills

Technical Skills Languages ... • System Verilog • VHDL • C • C++ • Perl and TCL Verification Tools ... • Incisive • NC-sim • SimVision • VCS • SILOS • Modelsim & Formality Verification Me... • Altera Quartus • Xilinx Vivado • ISE Programming Languages C • C++ and MATLAB Protocols & Standards... • DDR & SDRAM Hardware ... • Stratix-IV custom board • Logic analyzer • Digital storage oscilloscope and Oscillo... • Windows XP and MacOS Assembly Languages ...

Resumes

Karan Methe Photo 1

Senior Design Verification Engineer

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Location:
5917 Mayhews Landing Rd, Newark, CA 94560
Industry:
Semiconductors
Work:
SanDisk Corporation - San Jose since Jul 2012
ASIC Design Engineer
SanDisk - San Francisco Bay Area Aug 2011 - May 2012
ASIC FPGA Intern
Video Clarity - San Jose,Campbell Jun 2011 - Aug 2011
Perl Developer
Kinetic-Hyundai Elevator Movement Technologies Ltd. Dec 2007 - Apr 2009
Jr.Executive Engineer
Education:
San Jose State University 2010 - 2012
Masters, Electrical Engineering Sinhgad college of engineering 2003 - 2007
B.E., Electronics & Telecommunications Vidyapeeth Highschool 1990 - 2001
Skills:
Verilog
Fpga
Modelsim
Rtl Design
Systemverilog
Asic
Soc
C
Firmware
Xilinx
Perl
Functional Verification
Vhdl
Debugging
Static Timing Analysis
Rtl Coding
Altera Quartus
Analog
Ncsim
Application Specific Integrated Circuits
Quartus
Vlsi
Field Programmable Gate Arrays
Synopsys Tools
Microcontrollers
Circuit Design
Digital Electronics
Amba Ahb
Code Coverage
Assembly Language
Logic Synthesis
Eda
Logic Design
Universal Verification Methodology
Python
Interests:
New Technologies
Digital Photography
Karan Methe Photo 2

Karan Methe

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Karan Methe Photo 3

Karan Methe San Jose, CA

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Work:
SanDisk Corporation

Jul 2012 to 2000
ASIC Design Engineer II SanDisk Corporation

Aug 2011 to May 2012
ASIC FPGA Intern Video Clarity Inc. Campbell
San Jose, CA
Jun 2011 to Aug 2011
Perl Developer Kinetic-Hyundai Elevator & Movement Technologies Ltd

Dec 2007 to Apr 2009
Jr. Executive Engineer, Service Department
Education:
San Jose State University
Aug 2010 to May 2012
Master of Science in Electrical Engineering Pune University
Sep 2003 to May 2007
Bachelor of Engineering in Electronics & Telecommunications
Skills:
Technical Skills Languages Verilog, System Verilog, VHDL, C, C++, Perl and TCL Verification Tools Verdi3, Incisive, NC-sim, SimVision, VCS, SILOS, Modelsim & Formality Verification Methodologies OVM/UVM (basics) Synthesis & Place n route Tools Synplify Premier, Altera Quartus, Xilinx Vivado, ISE Programming Languages C, C++ and MATLAB Protocols & Standards eMMC 4.5/5.0 and AMBA-3 AHB protocols, DDR & SDRAM Hardware HAPS-70 Virtex-7 board, Stratix-IV custom board, Logic analyzer, Digital storage oscilloscope and Oscilloscope Operating Systems UNIX/LINUX, Windows XP and MacOS Assembly Languages 8051 & 8086
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