Karl Jacobs

US Patent:

6396339, May 28, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/605932

Inventors:

Karl H. Jacobs - Torrington CT

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330 9, 330256

Abstract:

An operational amplifier trim circuit architecture that compensates for fabrication process and temperature drift mismatches reflected to the input as input offset voltage errors without additional temperature compensation circuitry. The operational amplifier includes a first input signal and second input signal applied to an input circuit stage. The input circuit stage amplifies the first input signal differentially with respect to the second input stage and generates a differential current which in turn is applied to a first current path and a second current path. The first current path and second current path have well-matched trim circuits. The first current trim applies a trim current to the first current path, and the second current trim applies a trim current to the second current path. The trim current includes an offset current that is well-matched on both the first current trim path and the second current trim path and, in addition, may have a trim offset current that is present on the first trim current and not on the second trim current or vice versa, depending on the actual mismatch requiring correction on the particular device being trimmed. Thus, since both the first current path and the second current path see identical offset currents that are influenced by temperature variations in the same manner, the input offset voltage of the operational amplifier will have minimum drift over temperature variations.

US Patent:

7061291, Jun 13, 2006

Filed:

Dec 22, 2003

Appl. No.:

10/743171

Inventors:

Karl H. Jacobs - Pleasant Valley CT, US
Robert Neidorff - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 5/12

US Classification:

327170, 327 95

Abstract:

Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +V, the level shifter provides a voltage to the input resistor that ramps up from −Vto 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to −V, thereby providing a negative output supply voltage −Vwith a slew rate that linearly tracks the slew rate of the master positive output supply.

US Patent:

7463469, Dec 9, 2008

Filed:

Feb 2, 2006

Appl. No.:

11/346104

Inventors:

Karl H. Jacobs - Pleasant Valley CT, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 7/00
H02H 3/00

US Classification:

361 937

Abstract:

A system and method for responding to a current overload condition in a power switch provides a class D topology that applies a current sink or current source to the gate of the power switch. The current sink or source decreases or increases current flowing through the power switch to regulate power switch output current in the event of an overload. A timer for current regulation can be provided to shut off the power switch if the overload condition persists. A set of differently rated switches can be used separately or together to provide a range of current regulation response, from a wide regulation range with a fast response, to a narrow regulation range with a slow response. The system provides a rapid response to an overload condition and output current regulation without disabling the power switch to overcome short term overloads.