Karthik R Neravetla from 1649 Indigo Oak Ln, San Jose, CA 95121, age 54, Phone: 4082217161

Phase Locked Loop Clock Divider Utilizing A High Speed Programmable Linear Feedback Shift Register With A Two Stage Pipeline Feedback Path
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US Patent:

6556647, Apr 29, 2003
Filed:

May 1, 2002
Appl. No.:

10/137079
Inventors:

Karthik Reddy Neravetla - San Jose CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G11C 1900
US Classification:

377 70, 377 75, 377 80, 377 81
Abstract:

An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of âpre-loadâ flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.

Fractional Clock Divider Using Digital Techniques
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US Patent:

6861881, Mar 1, 2005
Filed:

Sep 29, 2003
Appl. No.:

10/674874
Inventors:

Karthik R. Neravetla - San Jose CA, US
Annie Wang - Mountain View CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H03K021/00
US Classification:

327115, 327117, 377 48
Abstract:

A fractional clock divider system and method is provided. The clock divider is configured to provide an output clock signal in response to an input clock signal. The frequency of the output clock signal may be an integral or fractional division of the input clock signal. The output frequency is equal to: (ref_freq*2)/mul, where ref_freq is the frequency of the input clock signal, and mul is a selected integer that is greater than one. The positive and negative edges of the input clock are counted to provide a positive count and a negative count respectively. A table is configured to store preselected reference values. A logic circuit is configured to control the output clock signal such that an appropriate clock transition occurs in the output clock signal when the positive and negative count reach the corresponding preselected reference values.

Phase Locked Loop Clock Divider Utilizing A High Speed Programmable Linear Feedback Shift Register
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US Patent:

6424691, Jul 23, 2002
Filed:

Sep 21, 2001
Appl. No.:

09/960590
Inventors:

Karthik R. Neravetla - San Jose CA
Steven J. Kommrusch - Fort Collins CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H03K 2100
US Classification:

377 48, 377 80, 377 81
Abstract:

An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.

Independent Asynchronous Framework For Embedded Subsystems
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US Patent:

20160132097, May 12, 2016
Filed:

Nov 6, 2014
Appl. No.:

14/535183
Inventors:

- San Diego CA, US
Eunjoo Hwang - San Jose CA, US
Karthik Reddy Neravetla - San Jose CA, US
Jen-Jung Hsu - San Diego CA, US
International Classification:

G06F 1/32
Abstract:

An integrated circuit is provided with an independent power framework for a first subsystem and another independent power framework for a processor subsystem that receives messages from the first subsystem.

Karthik R Neravetla