Katherine Elaine Brown

US Patent:

6650694, Nov 18, 2003

Filed:

Jun 30, 2000

Appl. No.:

09/607410

Inventors:

Katherine G. Brown - Coppell TX
Sundararajan Sriram - Plano TX
Francis Honore - Houston TX
Kang Lee - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 169

US Classification:

375150, 370342

Abstract:

A programmable, flexible, vector correlation engine for CDMA mobile and base station chip rate signal processing. A correlator co-processor (CCP) performs the de-spreading tasks for a RAKE receiver, early/late correlations for time tracking, and has provision for coherent accumulation of different lengths. The CCP also performs energy estimation and non-coherent accumulation functions. The CCP can also perform correlation functions required for delay profile estimation, and for search/acquisition functions. The same centralized Data Path is used to perform all these functions; a common controller generates signals into the Data Path in response to tasks initiated by a host processor (e. g. , DSP). The tasks written into the CCP are performed effectively in parallel by the CCP Data Path.

US Patent:

6721295, Apr 13, 2004

Filed:

Aug 25, 2000

Appl. No.:

09/648184

Inventors:

Katherine G. Brown - Coppell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 7216

US Classification:

370335, 370342, 370441, 370535, 370537, 370412, 710305, 327407

Abstract:

A slot-aligned IQ data buffer scheme has a third buffer that allows a processing engine to slide the selection of a vector to be processed so that it aligns with the framing of the data. This is particularly advantageous for CDMA and WCDMA systems where there are overlaying coded data streams, each with its own frame timing, since data is processed cleanly at boundaries in the data such that the processing hardware can be minimized. A first level of muxing selects a pair of buffers having the data to be processed from among three buffers. A second level of muxing selects the sample number required. The third level of muxing selects the correct chips for the alignment of the slot. The third stage is implemented with a barrel shifter to minimize hardware generally associated with use of multiplexing.

US Patent:

6792031, Sep 14, 2004

Filed:

Oct 18, 2000

Appl. No.:

09/691576

Inventors:

Sundararajan Sriram - Dallas TX
Yuan Kang Lee - Richardson TX
Katherine G. Brown - Coppell TX
Zhenguo Gu - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 169

US Classification:

375147, 370320, 370335, 370342, 398 78

Abstract:

A system and method for maintaining timing in a CDMA rake receiver has a global chip counter that counts CDMA signal chips as they arrive at the CDMA rake receiver. A local pseudo-noise (PN) sequence replica of the incoming CDMA signal is generated and used to perform a sliding window correlation of the locally generated PN sequence replica with the incoming signal to correlate the CDMA signal timing relative to stored CDMA signal chip counts. The PN sequence timing is maintained relative to GCC, which avoids having to keep track of absolute time within each Rake finger.

US Patent:

20080120189, May 22, 2008

Filed:

Oct 27, 2006

Appl. No.:

11/553888

Inventors:

Sumit Singh - Irving TX, US
Katherine Ricker Brown - Colleyville TX, US
Sanjiv Shah - Irving TX, US
Javier Martinez - Coppell TX, US
Venkateswara Nagarapu - Irving TX, US
Leena Naidu - Irving TX, US

Assignee:

MCI, LLC. - Basking Ridge NJ

International Classification:

G06Q 20/00

US Classification:

705 16, 705 26

Abstract:

An approach is provided for automating workflow. A sales order is received. One of a plurality of implementation centers is selected based on a rule. The sales order is stored in one of a plurality of queues that are mapped to the implementation centers.

US Patent:

62822306, Aug 28, 2001

Filed:

Sep 23, 1999

Appl. No.:

9/404082

Inventors:

Katherine G. Brown - Coppell TX
Zhengou Gu - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 1500
H04K 100
H04L 2730

US Classification:

375140

Abstract:

An LFRS (40, 50) calculates a PN sequence using Fibonacci form, such that when an offset is calculated from a known state, the bits of the new state comprise a block of sequence bits. Accordingly, to calculate a block having a length less than the length of the LFSR (40), all bits of the desired block can be calculated in a single offset calculation. If the block has a length greater than the length of the LFSR, one or more additional masks can be used to calculate the additional bits of the block sequence. Zero insertion is also supported.