Katherine C Norris

US Patent:

59435879, Aug 24, 1999

Filed:

Jun 25, 1997

Appl. No.:

8/882720

Inventors:

Robert R. Batterson - Manassas VA
Katherine Cecelia Norris - Milton VT
Paul David Sonntag - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438401

Abstract:

Offset alignment marks and a method of forming offset alignment marks within a kerf region of a semiconductor wafer in the manufacture of semiconductor devices includes the steps of forming a first track of a kerf and forming a second track of the kerf. The first track includes at least one alignment mark region having a first alignment mark disposed therein for use in an alignment of a first field of a first semiconductor chip active area. The second track includes at least one alignment mark region having a second alignment mark disposed therein for use in an alignment of a second field of a second semiconductor chip active area. The alignment mark regions of the first track and the second track are complementary and interlocking alignment mark regions extending across a centerline of the kerf and arranged in an offset manner with respect to one another along the kerf.

US Patent:

62591649, Jul 10, 2001

Filed:

Apr 1, 1999

Appl. No.:

9/283992

Inventors:

Robert R. Batterson - Manassas VA
Katherine Cecelia Norris - Milton VT
Paul David Sonntag - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23544

US Classification:

257797

Abstract:

Offset alignment marks and a method of forming offset alignment marks within a kerf region of a semiconductor wafer in the manufacture of semiconductor devices includes the steps of forming a first track of a kerf and forming a second track of the kerf. The first track includes at least one alignment mark region having a first alignment mark disposed therein for use in an alignment of a first field of a first semiconductor chip active area. The second track includes at least one alignment mark region having a second alignment mark disposed therein for use in an alignment of a second field of a second semiconductor chip active area. The alignment mark regions of the first track and the second track are complementary and interlocking alignment mark regions extending across a centerline of the kerf and arranged in an offset manner with respect to one another along the kerf.