Kathleen J Duncan

US Patent:

6597394, Jul 22, 2003

Filed:

Nov 9, 1998

Appl. No.:

09/188871

Inventors:

Kathleen A. Duncan - Santa Cruz CA
William S. Jacobs - Santa Cruz CA
Robert G. Taylor - Scotts Valley CA

Assignee:

Pictos Technologies, Inc. - Newport Beach CA

International Classification:

H04N 5228

US Classification:

3482221, 34823199, 3484031, 37524018, 37524019, 382248, 382250

Abstract:

A programmable image transform processor has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

US Patent:

6961084, Nov 1, 2005

Filed:

Oct 5, 2000

Appl. No.:

09/679854

Inventors:

Kathleen A. Duncan - Santa Cruz CA, US
Raymond S. Livingston - Bonny Doon CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H04N005/228
H04N005/76
H04N007/12
G06K009/36

US Classification:

3482221, 34823199, 3484031, 37524019, 382248

Abstract:

A programmable image transform system has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

US Patent:

20050160406, Jul 21, 2005

Filed:

Jan 12, 2005

Appl. No.:

11/035153

Inventors:

Kathleen Duncan - Santa Cruz CA, US
Raymond Livingston - Bonny Doon CA, US

International Classification:

G06F009/44

US Classification:

717127000

Abstract:

A programmable image transform system has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

US Patent:

20050195289, Sep 8, 2005

Filed:

Sep 9, 2004

Appl. No.:

10/936713

Inventors:

William Jacobs - Santa Cruz CA, US
Kathleen Duncan - Santa Cruz CA, US

International Classification:

H04N005/222

US Classification:

348223100

Abstract:

A method and apparatus is provided which obtains the temporal signature of artificial illuminants using a single imaging path, by controlling and reading the actual solid stage area imager. When using the solid-state area sensor to sample the temporal characteristics of artificial illuminants it may be necessary to greatly increase solid-state area sensor readout speed and to also increase the solid-state area sensors effective sensitivity to light. A method and apparatus is provided for discriminating artificial illuminants reliably through-the-lens (TTL) without the cost and bulkiness and other disadvantages of an additional sensor. This method and apparatus may be used independently or can be used in combination with the white pixel discrimination or scene analysis methods described earlier and embodied in the prior art.

US Patent:

57014507, Dec 23, 1997

Filed:

Apr 22, 1996

Appl. No.:

8/639243

Inventors:

Kathleen Anne Duncan - Santa Cruz CA

Assignee:

Seagate Technology, Inc. - Scotts Valley CA

International Classification:

G06F 944
G06F 1312

US Classification:

395595

Abstract:

A modular ATA hard disc controller includes a small on-chip ATA sequencer microprocessor having on-chip dedicated hardware to manage real-time events without host CPU intervention, without substantially degrading cost/performance for the resultant controller chip. To conserve IC chip space, a small instruction set for the on-chip ATA sequencer microprocessor is provided, wherein branch instructions are avoided. The instruction set causes execution only for a given data transfer direction (read or write), or executes always. On-chip task registers are coupled directly to the ATA sequencer microprocessor. This architecture minimizes host CPU bottlenecking by decoupling the host CPU from real-time events occurring on the AT bus, and by decoupling the local processor from the task registers. The resultant controller automatically receipts for all write data, handles task file updating and intersector handshaking, and host microprocessor queueing of the address of the next disc data block to be transferred.

US Patent:

56969317, Dec 9, 1997

Filed:

Sep 9, 1994

Appl. No.:

8/303415

Inventors:

Marvin Mang-Yin Lum - San Jose CA
Don Michael Robinson - San Jose CA
Prafulla Bollampali Reddy - Santa Cruz CA
Kathleen Anne Duncan - Santa Cruz CA

Assignee:

Seagate Technology, Inc. - Scotts Valley CA

International Classification:

G06F 1208

US Classification:

395440

Abstract:

A disc controller services a host "read" command, without intervention by the disc controller's microcontroller, if the requested data is found in the disc controller's cache. The disc controller stores at least one cache entry. Each cache entry includes an address, a logical Bit, a valid Bit and a set of four buffer parameters: upper limit address, base address, pointer to the sector count and sector count. Each host command is decoded by the disc controller, and if the command is a "read" command the address in the cache entry is compared against the address in the host command. If the addresses match and the cache entry address is marked as being valid by its Valid bit, a "cache hit" signal is generated and the disc controller starts transferring the data requested by the host without waiting for the disc controller's microprocessor to process the host command. In particular, a sequencer and data transfer circuitry automatically generate a host interrupt request signal and transfer to the host at least a subset of the requested set of data blocks specified by each read command when a cache hit signal is generated. The disc controller includes circuitry for updating the information stored in the cache entry so that said updated information stored in the cache entry identifies data blocks in the cache sequentially subsequent to those data blocks transferred to the host.