Kathleen F Perry

US Patent:

47896485, Dec 6, 1988

Filed:

Oct 28, 1985

Appl. No.:

6/791887

Inventors:

Melanie M. Chow - Poughquag NY
John E. Cronin - Milton VT
William L. Guthrie - Hopewell Junction NY
Carter W. Kaanta - Essex Junction VT
Barbara Luther - Devon PA
William J. Patrick - Newburgh NY
Kathleen A. Perry - Lagrangeville NY
Charles L. Standley - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21304
H01L 21306

US Classification:

437225

Abstract:

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization.

US Patent:

52468852, Sep 21, 1993

Filed:

Aug 20, 1992

Appl. No.:

7/933951

Inventors:

Bodil E. Braren - Hartsdale NY
Karen H. Brown - Yorktown Heights NY
Kathleen A. Perry - West Hills CA
Rangaswamy Srinivasan - Yorktown Heights NY
Alvin Sugerman - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100
H01L 2102
H01L 21302
H01L 21463

US Classification:

437225

Abstract:

A method for providing superior fill of features in semiconductor processing utilizes a laser ablation system. Deposition is obtained by ablating target materials which are driven off perpendicular to the target in the direction of the deposition surface. The method provides complete fill of high aspect ratio features with nominal heating of the substrate. Alloys and graded layers, as well as pure metals, can be deposited in low temperature patterned layers. In addition, the system has been used to achieve superior trench filling for isolation structures.