Kathryn Story Purcell

US Patent:

7243212, Jul 10, 2007

Filed:

Aug 6, 2004

Appl. No.:

10/913991

Inventors:

Kathryn Story Purcell - Mountain View CA, US
Ahmad R. Ansari - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/16

US Classification:

712 34, 712 32, 712 40

Abstract:

Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not ready to execute the instruction. Initiation of execution of the instruction by the controller is done while continuing to indicate to the processor that the controller is not ready to execute the instruction.

US Patent:

7346759, Mar 18, 2008

Filed:

Aug 6, 2004

Appl. No.:

10/912897

Inventors:

Ahmad R. Ansari - San Jose CA, US
Kathryn Story Purcell - Mountain View CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/76

US Classification:

712 34

Abstract:

Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

US Patent:

7546441, Jun 9, 2009

Filed:

Aug 6, 2004

Appl. No.:

10/912844

Inventors:

Ahmad R. Ansari - San Jose CA, US
Kathryn Story Purcell - Mountain View CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/00

US Classification:

712220, 712225

Abstract:

A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.

US Patent:

7590822, Sep 15, 2009

Filed:

Aug 6, 2004

Appl. No.:

10/912865

Inventors:

Kathryn Story Purcell - Mountain View CA, US
Ahmad R. Ansari - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/00

US Classification:

712 34, 712232

Abstract:

Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

US Patent:

7590823, Sep 15, 2009

Filed:

Aug 6, 2004

Appl. No.:

10/913231

Inventors:

Ahmad R. Ansari - San Jose CA, US
Kathryn Story Purcell - Mountain View CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/00
G06F 15/76

US Classification:

712 34, 712200, 712202

Abstract:

Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

US Patent:

7788470, Aug 31, 2010

Filed:

Mar 27, 2008

Appl. No.:

12/057353

Inventors:

Kathryn S. Purcell - Mountain View CA, US
Ahmad R. Ansari - San Jose CA, US
Gaurav Gupta - Santa Clara CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/00

US Classification:

712 34

Abstract:

A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

US Patent:

7865698, Jan 4, 2011

Filed:

Mar 27, 2008

Appl. No.:

12/057356

Inventors:

Kathryn S. Purcell - Mountain View CA, US
Ahmad R. Ansari - San Jose CA, US

Assignee:

Xilinix, Inc. - San Jose CA

International Classification:

G06F 9/30

US Classification:

712208, 712 34

Abstract:

A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-code that is not masked to determine whether the op-code is for a slave device. The decoding of the second portion is performed by a controller having a decoder, and the controller bridges the master device for communication with the slave device. The decoding of the first portion of the bits is performed by the slave device. The first portion of the bits identifies an instruction from a group of instructions, and the group of instructions uses a single configuration register of registers of the controller.

US Patent:

8185720, May 22, 2012

Filed:

Mar 5, 2008

Appl. No.:

12/043097

Inventors:

Ahmad R. Ansari - San Jose CA, US
Jeffery H. Appelbaum - San Mateo CA, US
Kam-Wing Li - San Jose CA, US
James J. Murray - Lost Gatos CA, US
Kathryn S. Purcell - Mountain View CA, US
Alex S. Warshofsky - Miami Beach FL, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/76

US Classification:

712 28, 712220

Abstract:

A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.