Kedar Patel - Fremont CA Alper Ilkbahar - San Jose CA Roy Scheuerlein - Cupertino CA Andrew J. Walker - Mountain View CA
Assignee:
Matrix Semiconductor, Inc. - Santa Clara CA
International Classification:
H01L 2976
US Classification:
257 67, 257206, 257369, 257393, 257324
Abstract:
A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
Method To Eliminate Inverse Narrow Width Effect In Small Geometry Mos Transistors
Jeffrey T. Watt - Palo Alto CA Kedar Patel - Fremont CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 2131
US Classification:
438773, 438431
Abstract:
A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.
High Density 3D Rail Stack Arrays And Method Of Making
Kedar Patel - Fremont CA, US Alper Ilkbahar - San Jose CA, US Roy Scheuerlein - Cupertino CA, US Andrew J. Walker - Mountain View CA, US
Assignee:
Matrix Semiconductor, Inc. - Santa Clara CA
International Classification:
H01L029/76
US Classification:
257213, 257 71
Abstract:
A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
Robert McDaniel - Palo Alto CA, US David C. Myles - Kensington CA, US Kedar Gautam Patel - Palo Alto CA, US Misty Piagentini - Fremont CA, US Zhan Wang - El Dorado Hills CA, US
2-Desmethyl ansamycins having a structure according to formula I, where R, R, R, R, Rand Rare as defined herein, and other 2-desmethyl ansamycins are useful as antiproliferative agents.
The invention provides strategies, methods, vectors, reagents, and systems for production of synthetic genes, production of libraries of such genes, and manipulation and characterization of the genes and corresponding encoded polypeptides. In one aspect, the synthetic genes can encode polyketide synthase polypeptides and facilitate production of therapeutically or commercially important polyketide compounds.
Cell-Free Synthesis Of Active Reprogramming Transcription Factors
William Yang - Stanford CA, US Kedar Patel - Fremont CA, US Yohannes T. Ghebremariam - Stanta Clara CA, US Ji Eun Lee - Menlo Park CA, US John P. Cooke - Palo Alto CA, US James Robert Swartz - Menlo Park CA, US
International Classification:
C12P 21/00
US Classification:
435 681
Abstract:
Compositions and methods are provided for the cell-free synthesis of active reprogramming factor polypeptides. The reprogramming factors may be synthesized as fusion proteins comprising a permeant domain, such as polyarginme. The cell free-synthesis may be conducted at about 25 C in a bacterial cell extract from genetically alterd cells having decreased endogenous protease activity Further, the proteins may comprise a fusion partner which enhances solubility and may be refolded on a column.
Method To Eliminate Inverse Narrow Width Effect In Small Geometry Mos Transistors
Jeffrey T. Watt - Palo Alto CA Kedar Patel - Fremont CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H01L 2176
US Classification:
438431
Abstract:
A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.
Greyscale Lithography Techniques For Manufacturing Field Plates
Methods for efficiently manufacturing field plates with one or more sloped profiles are described. The fabrication of a field plate structure may include the application of greyscale lithography techniques to enable the concurrent formation of one or more sloped surfaces of the field plate structure during one or more common processing steps. A technical benefit of manufacturing field plate structures that have one or more sloped surfaces using greyscale lithography is that fabrication costs may be substantially reduced by reducing the number of process steps required to form the field plate structures.
Name / Title
Company / Classification
Phones & Addresses
Kedar Patel President
INSYT Nonclassifiable Establishments · Real Estate Agent/Manager · Business Services at Non-Commercial Site
Senior Product Evaluation Engineer at ON Semiconductor
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Work:
ON Semiconductor - Santa Clara since Jan 2012
Senior Product Evaluation Engineer
ON Semiconductor - Santa Clara Jun 2011 - Dec 2011
Product Evaluation Engineer - Intern
BatchTest Systems - Santa Clara Jun 2010 - May 2011
R&D Engineer
Education:
San Jose State University 2009 - 2011
MS, Electrical Engineering
institute of Technology, Nirma University 2005 - 2009
B.Tech, Electronics and Communication Engineering
DNA2.0 since May 2013
Senior Scientist
Amyris Inc Jul 2010 - Apr 2013
Scientist (Biology)
Stanford University Sep 2005 - Jun 2010
Doctoral Researcher
Kosan Biosciences 2002 - 2005
Senior Research Associate
Stanford University Jan 2001 - Dec 2001
Research Assistant
Education:
Stanford University 2005 - 2010
PhD, Chemical Engineering
Stanford University 2000 - 2001
M.S., Chemical Engineering
University of Mumbai 1996 - 2000
B.E., Chemical Engineering
Jai Hind College 1994 - 1996
High School (12th Grade), Science
Vice President, FRAM Platform, Technology R&D at Cypress Semiconductor
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Cypress Semiconductor since May 2011
Vice President, FRAM Platform, Technology R&D
SanDisk Jan 2006 - May 2011
Sr. Manager, Product Engineering
Matrix Semiconductor May 2001 - Jan 2006
Manager, Process Integration & Yield
PDF Solutions Oct 2000 - May 2001
Consulting Engineer
Cypress Semiconductor Jul 1998 - Oct 2000
Sr. Technology Development Engineer
Education:
University of California, Berkeley
Doctor of Philosophy (Ph.D.), Electrical Engineering
University of California, Berkeley
Master of Science (M.S.), Electrical Engineering
University of California, Berkeley
Bachelor of Science (B.S.), Engineering Physics
Kedar Patel 1994 graduate of Clements High School in Sugar land, TX is on Memory Lane. Get caught up with Kedar and other high school alumni from Clements