Keith G Arnold

US Patent:

20210279388, Sep 9, 2021

Filed:

Mar 2, 2021

Appl. No.:

17/189621

Inventors:

- Santa Clara CA, US
Qing Zhu - Rowlett TX, US
Keith Arnold - Austin TX, US

Assignee:

PDF Solutions, Inc. - Santa Clara CA

International Classification:

G06F 30/27

Abstract:

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.