Keith M Bailey

US Patent:

6372526, Apr 16, 2002

Filed:

Apr 6, 1998

Appl. No.:

09/055458

Inventors:

Keith W. Bailey - Mesa AZ
Sury N. Darbha - Tempe AZ
Prosanto K. Mukerji - Phoenix AZ
Gary R. Lorenzen - Phoenix AZ

Assignee:

Semiconductor Components Industries LLC - Phoenix AZ

International Classification:

H01L 2166

US Classification:

438 15, 438110, 438112, 438123

Abstract:

A method of manufacturing semiconductor components ( ) includes assembling, packaging, and testing the semiconductor components ( ) while the semiconductor components ( ) are mounted on an adhesive layer ( ). The method of can also keep the semiconductor components ( ) mounted on the adhesive layer ( ) between each of the assembling, packaging, and testing steps.

US Patent:

55578420, Sep 24, 1996

Filed:

May 30, 1995

Appl. No.:

8/452754

Inventors:

Keith W. Bailey - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01R 4300

US Classification:

29827

Abstract:

A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).

US Patent:

55302840, Jun 25, 1996

Filed:

Mar 6, 1995

Appl. No.:

8/398830

Inventors:

Keith W. Bailey - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348
H01L 2952
H01L 2328

US Classification:

257670

Abstract:

A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).

US Patent:

6147410, Nov 14, 2000

Filed:

Mar 2, 1998

Appl. No.:

9/033188

Inventors:

Alexander J. Elliott - Tempe AZ
Timothy E. Meko - Chandler AZ
Gary R. Lorenzen - Phoenix AZ
Kent Lamar Kime - Phoenix AZ
Prosanto K. Mukerji - Phoenix AZ
Keith W. Bailey - Mesa AZ
William L. Fragale - Scottsdale AZ
Pablo Rodriguez - Gilbert AZ
George C. Chen - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348

US Classification:

257776

Abstract:

An electronic component includes a semiconductor substrate (101, 301, 401), an electrically conductive layer (102, 103, 302, 303, 402, 403) supported by the semiconductor substrate (101, 301, 401), and a lead (110, 120, 210, 310, 410, 420) having an electrical coupling portion (112, 122, 212, 312, 412, 422) coupled to and supported by the electrically conductive layer (102, 103, 302, 303, 402, 403) wherein the electrical coupling portion (112, 122, 212, 312, 412, 422) has at least one notch (115, 215, 315) adjacent to the electrically conductive layer (102, 103, 302, 303, 402, 403).