Keith Stewart Nelson

US Patent:

7927927, Apr 19, 2011

Filed:

Aug 13, 2001

Appl. No.:

09/928737

Inventors:

Son Ky Quan - Fountain Hills AZ, US
Samuel L. Coffman - Scottsdale AZ, US
Bruce Reid - Mesa AZ, US
Keith E. Nelson - Tempe AZ, US
Deborah A. Hagen - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/332

US Classification:

438137, 438460

Abstract:

A semiconductor package substrate () has an array of package sites (, and ) that are substantially identical. The entire array of package sites (, and ) is covered by an encapsulant (). The individual package sites (, and ) are singulated by sawing through the encapsulant () and the underlying semiconductor package substrate ().

US Patent:

54689104, Nov 21, 1995

Filed:

Jan 19, 1995

Appl. No.:

8/375061

Inventors:

James H. Knapp - Chandler AZ
Keith E. Nelson - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2328
H01L 2312
H05K 720
H05K 118

US Classification:

174 522

Abstract:

A method for making an improved semiconductor device package is provided. A semiconductor die (16) is attached to a supportive substrate (10, 12). A protective lid (20) is attached to the supportive substrate (10, 12), over the semiconductor die (16). The protective lid (20) is partially encapsulated with molding compound (28). The protective lid (20) prevents the molding compound (30) from contacting the semiconductor die (16), and associated wirebonded wires (18). A portion (30) of the protective lid (20) remains exposed. Thus, a molded package compatible with current product designs and assembly processes is provided, yet disadvantages caused by molding compound contacting the die (16) and wires (18) are avoided. Furthermore, the exposed protective lid (30) provides superior heat dissipation for the package.

US Patent:

58952292, Apr 20, 1999

Filed:

May 19, 1997

Appl. No.:

8/858756

Inventors:

Francis J. Carney - Gilbert AZ
George Amos Carson - Elk Grove Village IL
Phillip C. Celaya - Chandler AZ
Harry Fuerhaupter - Lombard IL
Frank Tim Jones - Chandler AZ
Donald H. Klosterman - Gilbert AZ
Cynthia M. Melton - Bolingbrook IL
James Howard Knapp - Chandler AZ
Keith E. Nelson - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2144
H01L 2148

US Classification:

438106

Abstract:

A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12). The mold (30) has a molding surface (34) that includes the surrounding region (28) and a mold surface (34) that faces the back face (24) and is spaced apart therefrom. A polymeric precursor (36) is dispensed into the mold cavity (32) and is formed against the molding surface (34) and the back face (24).

US Patent:

50068202, Apr 9, 1991

Filed:

Jul 3, 1989

Appl. No.:

7/374791

Inventors:

Jerry E. Prioste - Scottsdale AZ
Keith Nelson - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03H 738

US Classification:

333 33

Abstract:

An integrated circuit package having a low reflection input pin comprising a high frequency signal conductor internal to the semiconductor package is provided by coupling a first input pin to a second input pin with a conductive path, the conductive path having a constant characteristic impedance which matches the characteristic impedance of an external signal line which is coupled to the first input pin. A portion of the conductive path forms a bonding pad using for wire bonding, or other bonding technique, between the conductive path and a bonding pad of the integrated circuit. In this manner the impedance mismatch between an external signal conductor and the integrated circuit bonding pad is eliminated, and the total impedance mismatch between the semiconductor package and the external signal line is greatly reduced, resulting in higher frequency operation of the integrated circuit.

US Patent:

51820714, Jan 26, 1993

Filed:

Dec 14, 1990

Appl. No.:

7/627526

Inventors:

James H. Knapp - Gilbert AZ
Keith E. Nelson - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B29C 4502
B29C 4558

US Classification:

26427213

Abstract:

Molding carrier structures to leads of existing semiconductor packages is accomplished by molding at temperatures which maintain approximately matched thermal expansion between an encapsulating material and leads of the semiconductor package. The matched thermal expansion is provided by molding at temperatures below that which is required for glass transition of the encapsulating material. Molding at such temperatures is facilitated by a molding assembly that has a molding pot with an irregular shaped bottom which fluidizes the encapsulating material at low temperatures. Molding at temperatures that essentially match thermal expansion between the package's leads and the encapsulating material prevents damaging the leads of the package.

US Patent:

59006692, May 4, 1999

Filed:

Jun 30, 1997

Appl. No.:

8/886100

Inventors:

James H. Knapp - Chandler AZ
Keith E. Nelson - Tempe AZ
Les Ticey - Gilbert AZ
Kevin J. Foley - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2328

US Classification:

257701

Abstract:

A substrate having a vent (20) and a method of forming the vent (20). A substrate (11) has conductive traces (14) and a semiconductor chip attach pad (17) on a top surface and conductive traces (12) and a bonding pad (13) on the bottom surface. A masking layer (18) is formed over the substrate (11) and openings are formed in the masking layer (18) to expose the conductive traces (14) and a semiconductor chip attach pad (17). The vent (20) is formed in the masking layer (18). A semiconductor chip (31) is mounted to the semiconductor chip attach pad (17). During a step of encapsulating the semiconductor chip (31) with a mold compound, the vent (20) provides pressure relief.

US Patent:

59733373, Oct 26, 1999

Filed:

Aug 25, 1997

Appl. No.:

8/917121

Inventors:

James H. Knapp - Chandler AZ
Dwight L. Daniels - Mesa AZ
Keith E. Nelson - Tempe AZ
Brian A. Webb - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2329
H01L 2348

US Classification:

257 99

Abstract:

A semiconductor device (10) coupled to ball grid array substrate (11) and encapsulated by an optically transmissive material (29, 31). The ball grid array substrate (11) has conductive interconnects (14) and a semiconductor receiving area (17) on a top surface and solder pads (13) on a bottom surface. An optoelectronic component (24) is mounted on the semiconductor receiving area (17) and encapsulated with the optically transmissive material (29, 31). Solder balls (18) are formed on the solder pads (13).

US Patent:

57767980, Jul 7, 1998

Filed:

Sep 4, 1996

Appl. No.:

8/708296

Inventors:

Son Ky Quan - Fountain Hills AZ
Samuel L. Coffman - Scottsdale AZ
Bruce Reid - Mesa AZ
Keith E. Nelson - Tempe AZ
Deborah A. Hagen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438112

Abstract:

A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).