Keith Douglas Short

US Patent:

6460122, Oct 1, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409929

Inventors:

Noel S. Otterness - Boulder CO
William A. Brant - Boulder CO
Keith E. Short - Lafayette CO
Joseph G. Skazinski - Bertoud CO

Assignee:

International Business Machine Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711154, 711122, 711130, 711216

Abstract:

This inventive provides a multiple level cache structure and multiple level caching method that distributes I/O processing loads including caching operations between processors to provide higher performance I/O processing, especially in a server environment. A method of achieving optimal data throughput by taking full advantage of multiple processing resources is disclosed. A method for managing the allocation of the data caches to optimize the host access time and parity generation is disclosed. A cache allocation for RAID stripes guaranteed to provide fast access times for the XOR engine by ensuring that all cache lines are allocated from the same cache level is disclosed. Allocation of cache lines for RAID levels which do not require parity generation and are allocated in such manner as to maximize utilization of the memory bandwidth is disclosed. Parity generation which is optimized for use of the processor least utilized at the time the cache lines are allocated, thereby providing for dynamic load balancing amongst the multiple processing resources, is disclosed. An inventive cache line descriptor for maintaining information about which cache data pool the cache line resides within, and an inventive cache line descriptor which includes enhancements to allow for movement of cache data from one cache level to another is disclosed.

US Patent:

6578158, Jun 10, 2003

Filed:

Oct 28, 1999

Appl. No.:

09/429523

Inventors:

William G. Deitz - Niwot CO
Keith Short - LaFayette CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 11, 714 5

Abstract:

A method and apparatus for controlling a memory system comprising a plurality of controllers connected by a fibre channel arbitrated loop to provide transparent failover and failback mechanisms for failed controllers. The controllers are adapted to transfer data between a data storage system and at least one host computer in response to instructions therefrom. In the method, a unique identifier is provided to each controller. The operation of the controllers is then monitored and, when a failed controller is detected, a failover procedure is performed on a surviving controller. The failover procedure includes disabling the failed controller and instructing the surviving controller to assume the identity of the failed controller. Thus, the surviving controller is capable of responding to instructions addressed to it and instructions addressed to the failed controller, and the failure of the failed controller is transparent to the host computer. A computer program and a computer program product for implementing the method are also provided.

US Patent:

7721260, May 18, 2010

Filed:

Sep 8, 2004

Appl. No.:

10/711287

Inventors:

Keith Edward Short - Lafayette CO, US
Joseph G. Skazinski - Berthoud CO, US

Assignee:

Kozio, Inc. - Longmont CO

International Classification:

G06F 9/44

US Classification:

717124, 717125, 717126, 717127, 717128

Abstract:

A system and method for testing input and output paths connected to an embedded processor. Specialized test software operating on the embedded processor creates one or more test workers or threads, each having a specific routine to perform, which are executed in parallel, stressing various communication paths. The results may be analyzed to help in many different ways during the life cycle of the device with the embedded controller.

US Patent:

20050120340, Jun 2, 2005

Filed:

Sep 9, 2004

Appl. No.:

10/937117

Inventors:

Joseph Skazinski - Berthoud CO, US
Keith Short - LaFayette CO, US

International Classification:

G06F009/45

US Classification:

717140000

Abstract:

The apparatus includes an input module for receiving hardware description data. The hardware description data describes hardware components of an embedded system. The apparatus also includes a build module for generating a board support layer for interfacing with the hardware components. The system may include the apparatus, an automation server coupled to a communications network, and a graphical user interface configured to display selectable icons representative of hardware elements from a plurality of hardware element icons, organize the selected icons into a hardware design, and generate hardware description data from the hardware design. The method includes receiving hardware description data describing hardware components of an embedded system, generating an embedded system board support layer in response to the described hardware description data for interfacing with the hardware components, and compiling the embedded system board support layer into executable code.