Keith A Thompson

US Patent:

53394151, Aug 16, 1994

Filed:

Nov 9, 1992

Appl. No.:

7/973598

Inventors:

Robert E. Strout - Livermore CA
George A. Spix - Eau Claire WI
Jon A. Masamitsu - Livermore CA
David M. Cox - Livermore CA
Gregory G. Gaertner - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Keith J. Thompson - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 946

US Classification:

395650

Abstract:

On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.

US Patent:

62025694, Mar 20, 2001

Filed:

Aug 3, 1999

Appl. No.:

9/365718

Inventors:

Michael G. Bailey - Woodbury MN
Kenneth Holz - Hastings MN
Keith G. Thompson - Cottage Grove MN

Assignee:

Bailey Nurseries, Inc. - St. Paul MN

International Classification:

B65D 1938

US Classification:

108 535

Abstract:

A stackable pallet system comprises a plurality of pallets used for holding and transporting various items, including potted plants such as potted trees, flowers, bushes, etc. When the pallets are to be stacked, two pairs of spacer pipes can be used on a first pallet extending upwardly therefrom. Two elongated saddles are then coupled, one to each pair of spacer pipes, such that the saddles extend between and unite the upper ends of the pairs of spacer pipes. The saddles comprise an upwardly facing, shallow channel which is sized to be slightly larger than at least a portion of the fork pockets contained on the pallet. A second pallet can be lowered down onto a first pallet with the fork pockets, or at least a portion of the fork pockets, being received in the saddle channels. Various containment rings can be coupled to the pipes, in place of or in addition to the saddles, to allow longer trees to be carried on the pallets or to allow double stacking of potted plants on a single pallet.

US Patent:

61956767, Feb 27, 2001

Filed:

Jan 11, 1993

Appl. No.:

8/003000

Inventors:

George A. Spix - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Stuart W. Hawkinson - Eau Claire WI
Mark D. Johnson - Eau Claire WI
Jeremiah D. Burke - Eau Claire WI
Keith J. Thompson - Eau Claire WI
Gregory G. Gaertner - Eau Claire WI
Giacomo G. Brussino - Eau Claire WI
Richard E. Hessel - Altoona WI
David M. Barkai - Eau Claire WI
Steve S. Chen - Chippewa Falls WI
Steven G. Oslon - Chippewa Falls WI
Robert E. Strout - Livermore CA
Jon A. Masamitsu - Livermore CA
David M. Cox - Livermore CA
Linda J. O'Gara - Livermore CA
Kelly T. O'Hair - Livermore CA
David A. Seberger - Livermore CA
James C. Rasbold - Livermore CA
Timothy J. Cramer - Pleasanton CA
Don A. Van Dyke - Pleasanton CA
Ashok Chandramouli - Fremont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 946

US Classification:

709107

Abstract:

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

US Patent:

53903293, Feb 14, 1995

Filed:

Jul 20, 1994

Appl. No.:

8/277776

Inventors:

Gregory G. Gaertner - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Keith J. Thompson - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MO

International Classification:

G06F 946

US Classification:

395650

Abstract:

A method of providing fast and efficient kernel functions including those usually performed by kernel daemons and other kernel processes such as those which service interrupts. The method consists of using minimal-context processes that carry only the system-related information needed to do the work they are created to do. Compared to the full-context processes presently used to do kernel functions, minimal-context processes are created quickly and switch economically. If associated with a work queue, the minimal-context process performs a series of tasks within a single active session. If no queue is used, a minimal-context process can wake up and accomplish a single task rapidly. The method generally relates to kernel-based operating systems.

US Patent:

52029883, Apr 13, 1993

Filed:

Aug 23, 1990

Appl. No.:

7/571951

Inventors:

George A. Spix - Eau Claire WI
Gregory G. Gaertner - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Keith J. Thompson - Eau Claire WI

Assignee:

Supercomputer Systems Limited Partnership - Eau Claire WI

International Classification:

G06F 1516

US Classification:

395650

Abstract:

Communication among processors having differing operating speeds by providing wake queues in which slower processors can queue entries, access to which by multiple concurrent producers and multiple concurrent consumers is synchronized or controlled using global registers. When a faster processor executes a kernel process for handling a wake queue, an entry is fetched from the wake queue and information stored in the entry is used to process the entry.

US Patent:

51797020, Jan 12, 1993

Filed:

Jun 11, 1990

Appl. No.:

7/537466

Inventors:

George A. Spix - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Stuart W. Hawkinson - Eau Claire WI
Mark D. Johnson - Eau Claire WI
Jeremiah D. Burke - Eau Claire WI
Keith J. Thompson - Eau Claire WI
Gregory G. Gaertner - Eau Claire WI
Giacomo G. Brussino - Eau Claire WI
Richard E. Hessel - Altoona WI
David M. Barkai - Eau Claire WI
Steve S. Chen - Chippewa Falls WI
Steven G. Oslon - Chippewa Falls WI
Robert E. Strout - Livermore CA
Jon A. Masamitsu - Livermore CA
David M. Cox - Livermore CA
Linda J. O'Gara - Livermore CA
Kelly T. O'Hair - Livermore CA
David A. Seberger - Livermore CA
James C. Rasbold - Livermore CA
Timothy J. Cramer - Pleasanton CA
Don A. Van Dyke - Pleasanton CA
Ashok Chandramouli - Fremont CA

Assignee:

Supercomputer Systems Limited Partnership - Eau Claire WI

International Classification:

G06F 946

US Classification:

395650

Abstract:

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

US Patent:

54524520, Sep 19, 1995

Filed:

Jun 4, 1993

Appl. No.:

8/072655

Inventors:

Gregory G. Gaetner - Eau Claire WI
George A. Spix - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Keith J. Thompson - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 946

US Classification:

395650

Abstract:

Method for enabling each of several processors in a multi-processing operating system to schedule processes it will execute without a supervisory scheduler. The processes are executed on the basis of priorities assigned to the processes. More than one processor can schedule processes simultaneously so long as each processor schedules processes having different priority levels from those being processed by another processor.