Kelly Joseph Fitzpatrick

US Patent:

6417788, Jul 9, 2002

Filed:

Mar 9, 2001

Appl. No.:

09/803401

Inventors:

Peter McEwen - Santa Clara CA
Kelly K Fitzpatrick - Sudbury MA
Bahjat M. Zafer - Sunnyvale CA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

H03M 700

US Classification:

341 59, 341 94, 360 40, 714701

Abstract:

A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encodingâone easy to implementâis applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

US Patent:

6446236, Sep 3, 2002

Filed:

Oct 13, 1999

Appl. No.:

09/418191

Inventors:

Peter McEwen - Santa Clara CA
Hossein Sedarat - Stanford CA
Kelly Fitzpatrick - Sudbury MA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

H03M 1303

US Classification:

714795, 714763, 714792, 714796, 375262, 375265, 375341, 360 53

Abstract:

A scheme (apparatus and methods) for recovering encoded data from a data signal representing one or more data symbols and subject to random errors and transient errors. A system in accordance with this scheme includes a transient error detector, a reliability detector, an erasure flagger, and a decoder. The transient error detector is coupled to receive the data signal and is configured to identify one or more characteristics (e. g. , a starting location and a midpoint location) of a transient error (e. g. , a TA) in the data signal. The reliability detector is configured to compute a reliability metric for each data symbol. The erasure flagger identifies erasures based upon signals received from the transient error detector and the reliability detector. The decoder is configured to treat a data symbol as an erasure or as a valid data symbol based upon the output of the erasure flagger.

US Patent:

6732328, May 4, 2004

Filed:

Jul 12, 1999

Appl. No.:

09/352160

Inventors:

Peter McEwen - Santa Clara CA
Kelly Fitzpatrick - Westboro MA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

H03M 1303

US Classification:

714795, 714792, 375341, 375265

Abstract:

A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

US Patent:

7089483, Aug 8, 2006

Filed:

Mar 4, 2004

Appl. No.:

10/793414

Inventors:

Peter McEwen - Santa Clara CA, US
Kelly Fitzpatrick - Westboro MA, US

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

H03M 13/03

US Classification:

714795, 714792, 375341, 375265

Abstract:

A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

US Patent:

7607072, Oct 20, 2009

Filed:

Jan 28, 2005

Appl. No.:

11/045585

Inventors:

Jonathan James Ashley - Los Gatos CA, US
Kelly Knudson Fitzpatrick - Sudbury MA, US
Erich Franz Haratsch - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 13/00

US Classification:

714792, 714795, 714800

Abstract:

Methods and apparatus are provided for performing Soft-Output Viterbi Algorithm (SOVA) detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

US Patent:

7865814, Jan 4, 2011

Filed:

Aug 26, 2009

Appl. No.:

12/547921

Inventors:

Jonathan James Ashley - Los Gatos CA, US
Kelly Knudson Fitzpatrick - Sudbury MA, US
Erich Franz Haratsch - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 13/03

US Classification:

714792, 714795, 714806

Abstract:

A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period. The disclosed path metric difference computation unit comprises path metric difference generators for generating a path metric difference Δfor a second single-step-trellis period based on a difference between the first path and the second path, and a path metric difference Δfor a first single-step-trellis period based on a difference between the first path and the third path, wherein intermediate path metric values or intermediate path metric difference values are reused to generate the path metric differences Δor Δ.

US Patent:

7937649, May 3, 2011

Filed:

Aug 26, 2009

Appl. No.:

12/547888

Inventors:

Jonathan James Ashley - Los Gatos CA, US
Kelly Knudson Fitzpatrick - Sudbury MA, US
Erich Franz Haratsch - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 13/03

US Classification:

714792, 714795, 714786

Abstract:

A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.

US Patent:

8250431, Aug 21, 2012

Filed:

Jul 30, 2009

Appl. No.:

12/512235

Inventors:

Shaohua Yang - Santa Clara CA, US
Zongwang Li - San Jose CA, US
Weijun Tan - Longmont CO, US
Kelly Fitzpatrick - Sudbury MA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03M 13/00

US Classification:

714755, 714758, 714786, 714752, 714763, 714780, 714794, 714795, 375262, 375341

Abstract:

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.