Kelly Shea Taylor

Address:

9824 Parkford Dr, Dallas, TX 75238

VIN:

2HJYK16587H524178

Make:

HONDA

Model:

RIDGELINE

Year:

2007

US Patent:

6351039, Feb 26, 2002

Filed:

May 28, 1998

Appl. No.:

09/087457

Inventors:

Changming Jin - Plano TX
Kelly J. Taylor - Allen TX
Wei William Lee - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257759, 257760, 438623, 438624

Abstract:

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

US Patent:

6465350, Oct 15, 2002

Filed:

Oct 12, 2000

Appl. No.:

09/689077

Inventors:

Kelly J. Taylor - Allen TX
Wei-Yan Shih - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438688, 438627, 438629, 438637, 438672, 438675, 438643, 438660

Abstract:

A method for forming a thin aluminum-nitride film ( ). Solid hydrazine cyanurate is heated to produce in-situ hydrazine (N H ). The in-situ hydrazine reacts with a previously deposited ailminum layer ( ) to form aluminum-nitride ( ).

US Patent:

6645804, Nov 11, 2003

Filed:

May 1, 2002

Appl. No.:

10/136642

Inventors:

F. Scott Johnson - Richardson TX
Luigi Columbo - Dallas TX
Doug Prinslow - McKinney TX
Kelly Taylor - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438238, 438381

Abstract:

Disclosed is a system for fabricating an integrated circuit capacitor ( ). An electrode layer ( ) is formed in the integrated circuit. An anti-reflective coating ( ) is deposited over the electrode layer ( ). An electrode top plate ( ) is formed over the anti-reflective coating ( ).

US Patent:

6803641, Oct 12, 2004

Filed:

Aug 11, 2003

Appl. No.:

10/638596

Inventors:

Satyavolu S. Papa Rao - Garland TX
Asad M. Haider - Dallas TX
Kelly Taylor - Allen TX
Ed Burke - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257532, 257306, 3613062

Abstract:

Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

US Patent:

6876021, Apr 5, 2005

Filed:

Nov 25, 2002

Appl. No.:

10/303560

Inventors:

J. Scott Martin - Garland TX, US
Scott R. Summerfelt - Garland TX, US
Theodore S. Moise - Dallas TX, US
Kelly J. Taylor - Allen TX, US
Luigi Colombo - Dallas TX, US
Sanjeev Aggarwal - Plano TX, US
Sirisha Kuchimanchi - Dallas TX, US
K. R. Udayakumar - Dallas TX, US
Lindsey Hall - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L031/119

US Classification:

257295, 257296

Abstract:

The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

US Patent:

6919233, Jul 19, 2005

Filed:

Dec 31, 2002

Appl. No.:

10/335333

Inventors:

Satyavolu S. Papa Rao - Garland TX, US
Asad M. Haider - Dallas TX, US
Kelly Taylor - Allen TX, US
Ed Burke - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/62

US Classification:

438128, 438240, 438396

Abstract:

Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

US Patent:

7001821, Feb 21, 2006

Filed:

Nov 10, 2003

Appl. No.:

10/705039

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US
Theodore S. Moise - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/20

US Classification:

438396, 438253, 438 3, 257295, 257296

Abstract:

Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

US Patent:

7144808, Dec 5, 2006

Filed:

Jun 13, 2005

Appl. No.:

11/151154

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438675, 438648, 438643, 438637, 438638, 438639, 438652, 438653, 438654, 438655, 438656, 438658, 438659, 438677, 438678, 438679, 438680, 438672, 438668, 438642, 438644, 438626, 438627, 438628, 438629, 438622, 438623, 438624, 438631, 438632, 438633, 438635, 257E21143

Abstract:

The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.