Kelly A Taylor

US Patent:

6351039, Feb 26, 2002

Filed:

May 28, 1998

Appl. No.:

09/087457

Inventors:

Changming Jin - Plano TX
Kelly J. Taylor - Allen TX
Wei William Lee - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257759, 257760, 438623, 438624

Abstract:

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

US Patent:

6645804, Nov 11, 2003

Filed:

May 1, 2002

Appl. No.:

10/136642

Inventors:

F. Scott Johnson - Richardson TX
Luigi Columbo - Dallas TX
Doug Prinslow - McKinney TX
Kelly Taylor - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438238, 438381

Abstract:

Disclosed is a system for fabricating an integrated circuit capacitor ( ). An electrode layer ( ) is formed in the integrated circuit. An anti-reflective coating ( ) is deposited over the electrode layer ( ). An electrode top plate ( ) is formed over the anti-reflective coating ( ).

US Patent:

7001821, Feb 21, 2006

Filed:

Nov 10, 2003

Appl. No.:

10/705039

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US
Theodore S. Moise - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/20

US Classification:

438396, 438253, 438 3, 257295, 257296

Abstract:

Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

US Patent:

7144808, Dec 5, 2006

Filed:

Jun 13, 2005

Appl. No.:

11/151154

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438675, 438648, 438643, 438637, 438638, 438639, 438652, 438653, 438654, 438655, 438656, 438658, 438659, 438677, 438678, 438679, 438680, 438672, 438668, 438642, 438644, 438626, 438627, 438628, 438629, 438622, 438623, 438624, 438631, 438632, 438633, 438635, 257E21143

Abstract:

The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

US Patent:

7153706, Dec 26, 2006

Filed:

Apr 21, 2004

Appl. No.:

10/829053

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US
Lindsey Hall - Plano TX, US
Satyavolu Srinivas Papa Rao - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438 3, 438240, 438633

Abstract:

The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (), among other elements, includes a substantially planar ferroelectric dielectric layer () located over a first electrode layer (), wherein the substantially planar ferroelectric dielectric layer () has an average surface roughness of less than about nm. The ferroelectric capacitor () further includes a second electrode layer () located over the substantially planar ferroelectric dielectric layer ().

US Patent:

7332425, Feb 19, 2008

Filed:

May 11, 2005

Appl. No.:

11/126460

Inventors:

Asad M. Haider - Plano TX, US
Kelly J. Taylor - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/4763

US Classification:

438618, 438197, 438680, 438905, 257E21017, 257E21304, 257E21421, 257E21435

Abstract:

The present invention provides a method of forming a interconnect barrier layer. In the method, physical vapor deposition of barrier material is performed within an opening located in a dielectric layer of a substrate. RF plasma etching of the barrier material that is deposited in the opening occurs simultaneously with conducting the physical vapor deposition of the barrier material.

US Patent:

7514734, Apr 7, 2009

Filed:

Sep 6, 2005

Appl. No.:

11/220292

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US
Theodore S. Moise - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/76

US Classification:

257295, 257310, 257E21009, 257E21021, 438 3, 438201, 438257, 438593

Abstract:

Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

US Patent:

7361949, Apr 22, 2008

Filed:

Jan 28, 2005

Appl. No.:

11/046568

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/76

US Classification:

257295, 257300

Abstract:

An embodiment of the invention is a method of fabricating a haze free, phase pure, PZT layer, , where a lead rich PZT film, , is formed over a phase pure stoichiometric PZT film,.