Kelly L Williams

US Patent:

7514276, Apr 7, 2009

Filed:

Aug 12, 2008

Appl. No.:

12/190395

Inventors:

Corey Elizabeth Yearous - Rochester MN, US
Phil Christopher Paone - Rochester MN, US
Kelly Lynn Williams - Rochester MN, US
David Paul Paulsen - Rochester MN, US
Gregory John Uhlmann - Rochester MN, US
Karl Robert Ericson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438 15, 438 14, 438 17, 438 18, 438108, 438126, 257E21511, 257E21606, 257E21705, 257E23004, 257E23019

Abstract:

The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.

US Patent:

7868391, Jan 11, 2011

Filed:

Jun 4, 2009

Appl. No.:

12/478098

Inventors:

Phil Christopher Felice Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119
H01L 27/01
H01L 27/12
H01L 31/0392
H01L 23/62

US Classification:

257369, 257335, 257338, 257341, 257350, 257351, 257357, 257371, 257401, 257E27026, 257E27027, 257E27059, 257E2706, 257E27062, 257E27064

Abstract:

A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

US Patent:

8114747, Feb 14, 2012

Filed:

Nov 10, 2010

Appl. No.:

12/943146

Inventors:

Phil Christopher Felice Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438300, 438303, 438305, 438481, 257327, 257E21634

Abstract:

A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

US Patent:

8384414, Feb 26, 2013

Filed:

Feb 22, 2011

Appl. No.:

13/031748

Inventors:

Karl R. Erickson - Rochester MN, US
Phil C. Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Gregory J. Uhlmann - Rochester MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/00

US Classification:

326 8, 726 34, 713194

Abstract:

A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

US Patent:

8395186, Mar 12, 2013

Filed:

Jan 12, 2011

Appl. No.:

13/005059

Inventors:

Karl R. Erickson - Rochester MN, US
Phil C. Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Gregory J. Uhlmann - Rochester MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

257156, 438153, 257328, 257330, 257332

Abstract:

A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

US Patent:

8435851, May 7, 2013

Filed:

Jan 12, 2011

Appl. No.:

13/005089

Inventors:

Karl R. Erickson - Rochester MN, US
Phil C. Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Gregory J. Uhlmann - Rochester MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438212, 438153, 438156, 257330, 257332, 257350, 257E29262

Abstract:

A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

US Patent:

8456187, Jun 4, 2013

Filed:

Apr 21, 2011

Appl. No.:

13/091243

Inventors:

Karl R. Erickson - Rochester MN, US
Phil C. Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Gregory J. Uhlmann - Rochester MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/00

US Classification:

326 8

Abstract:

A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

US Patent:

8492207, Jul 23, 2013

Filed:

Apr 21, 2011

Appl. No.:

13/091259

Inventors:

Karl R. Erickson - Rochester MN, US
Phil C. Paone - Rochester MN, US
David P. Paulsen - Dodge Center MN, US
Gregory J. Uhlmann - Rochester MN, US
Kelly L. Williams - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/762

US Classification:

438149, 257E21703, 257529

Abstract:

A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.