Ken T Suyama from 18 Marbourne Dr, Mamaroneck, NY 10543, age 69, Phone: 9143816134

Vehicle Records

Ken Suyama
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Address:

18 Marbourne Dr, Mamaroneck, NY 10543
Phone:

9143816134
VIN:

WBAEH13507CR46312
Make:

BMW
Model:

6 SERIES
Year:

2007

Name / Title

Company / Classification

Phones & Addresses

Ken Suyama
President

Epoch Micro Electronics
Electrical Contrs

220 White Pln Rd STE 230, Tarrytown, NY 10591
9143328570, 9143664331

Ken Suyama
President , Treasurer , Director

Catalyst Foundation

Ken Suyama
Principal

EPOCH MICROELECTRONICS, INC
Mfg Electrical Measuring Instruments

7 Skyline Dr / SUITE 265, Hawthorne, NY 10532
7 Skyline Dr, Hawthorne, NY 10532

Ken Suyama
Owner, Principal

Heineken USA Inc
Ret Family Clothing

50 Main St, White Plains, NY 10606
9146819162

Resumes

Owner

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Location:

New York, NY

Industry:

Semiconductors

Work:

Epoch Microelectronics, Inc.
President at Epoch Microelectronics, Inc
Columbia University In the City of New York Jan 1989 - May 1998
Research Scientist
Epoch Microelectronics, Inc. Jan 1989 - May 1998
Owner

Education:

Columbia University 1989
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering Columbia University In the City of New York 1983 - 1988
Doctorates, Doctor of Philosophy, Electrical Engineering Columbia Engineering 1981 - 1983
Master of Science, Masters, Electrical Engineering University of California, Davis 1978 - 1980
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science Waseda High School 1974

Skills:

Ic
Integrated Circuit Design
Rf
Analog
Analog Circuit Design
Circuit Design
Semiconductors
Asic
Electrical Engineering
Electronics
Mixed Signal
Verilog
Hardware Architecture
Simulations
Pcb Design
Cmos
Radio Frequency
Integrated Circuits

Us Patents

Semiconductor Integrated Circuit Having Built-In Pll Circuit
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US Patent:

7015735, Mar 21, 2006
Filed:

Dec 19, 2003
Appl. No.:

10/739117
Inventors:

Yasuyuki Kimura - Maebashi, JP
Satoshi Shimizu - Maebashi, JP
Masakatsu Yokota - Takasaki, JP
Ken Suyama - Mamaroneck NY, US
Aleksander Dec - Tarrytown NY, US
Assignee:

Renesas Technology Corp. - Tokyo
Epoch Microelectronics, Inc. - Hawthorne NY
International Classification:

H03L 7/06
US Classification:

327157, 331 16, 375376
Abstract:

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i. e. , the charge pump circuits operate in opposite phase.

Semiconductor Integrated Circuit Having Built-In Pll Circuit
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US Patent:

7212047, May 1, 2007
Filed:

Oct 4, 2005
Appl. No.:

11/241995
Inventors:

Yasuyuki Kimura - Maebashi, JP
Satoshi Shimizu - Maebashi, JP
Masakatsu Yokota - Takasaki, JP
Ken Suyama - Mamaroneck NY, US
Aleksander Dec - Tarrytown NY, US
Assignee:

Renesas Technology Corp. - Tokyo
Epoch Microelectronics, Inc. - Hawthorne NY
International Classification:

H03L 7/06
US Classification:

327148, 327157
Abstract:

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i. e. , the charge pump circuits operate in opposite phase.

Embedded Structure Circuit For Vco And Regulator
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US Patent:

7336138, Feb 26, 2008
Filed:

Apr 28, 2006
Appl. No.:

11/412973
Inventors:

Tomomitsu Kitamura - Tokyo, JP
Ken Suyama - Hawthorne NY, US
Aleksander Dec - Hawthorne NY, US
Assignee:

Renesas Technology Corp. - Tokyo
Epoch Microelectronics, Inc. - Hawthorne NY
International Classification:

H03B 5/12
H03L 1/00
US Classification:

331186, 331117 R, 331117 FE, 331176
Abstract:

An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.

Semiconductor Integrated Circuit Having Built-In Pll Circuit
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US Patent:

7689191, Mar 30, 2010
Filed:

Mar 30, 2007
Appl. No.:

11/730236
Inventors:

Yasuyuki Kimura - Maebashi, JP
Satoshi Shimizu - Maebashi, JP
Masakatsu Yokota - Takasaki, JP
Ken Suyama - Mamaroneck NY, US
Aleksander Dec - Tarrytown NY, US
Assignee:

Renesas Technology Corp. - Tokyo
Epoch Microelectronics, Inc. - Hawthorne NY
International Classification:

H04B 7/00
US Classification:

455260, 455333, 375376, 331 25
Abstract:

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i. e. , the charge pump circuits operate in opposite phase.

Pll Circuit With Improved Phase Difference Detection
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US Patent:

7859344, Dec 28, 2010
Filed:

Apr 29, 2008
Appl. No.:

12/111458
Inventors:

Toshiya Uozumi - Tokyo, JP
Keisuke Ueda - Tokyo, JP
Mitsunori Samata - Tokyo, JP
Satoru Yamamoto - Tokyo, JP
Russell P Mohn - Tarrytown NY, US
Aleksander Dec - Tarrytown NY, US
Ken Suyama - Tarrytown NY, US
Assignee:

Renesas Electronics Corporation - Kanagawa
Epoch Microelectronics, Inc. - Tarrytown NY
International Classification:

H03L 7/00
US Classification:

331 1A, 331 25, 331 34, 331177 R, 327156, 375376
Abstract:

In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Oscillation Circuit And A Communication Semiconductor Integrated Circuit
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US Patent:

20040056725, Mar 25, 2004
Filed:

Sep 25, 2002
Appl. No.:

10/253922
Inventors:

Tomomitsu Kitamura - Takasaki, JP
Yasuyuki Kimura - Maebashi, JP
Ken Suyama - Mamaroneck NY, US
Aleksander Dec - Yonkers NY, US
International Classification:

H03L007/00
US Classification:

331/03600C
Abstract:

A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.

Semiconductor Integrated Circuit Having Built-In Pll Circuit
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US Patent:

20070273415, Nov 29, 2007
Filed:

Apr 4, 2007
Appl. No.:

11/730819
Inventors:

Yasuyuki Kimura - Maebashi, JP
Satoshi Shimizu - Maebashi, JP
Masakatsu Yokota - Takasaki, JP
Ken Suyama - Mamaroneck NY, US
Aleksander Dec - Tarrytown NY, US
International Classification:

H03L 7/06
US Classification:

327157000
Abstract:

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Pll Circuit
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US Patent:

20100097150, Apr 22, 2010
Filed:

Oct 16, 2008
Appl. No.:

12/252443
Inventors:

Keisuke Ueda - Tokyo, JP
Toshiya Uozumi - Tokyo, JP
Satoru Yamamoto - Tokyo, JP
Mitsunori Samata - Tokyo, JP
Russell P. Mohn - Tarrytown NY, US
Aleksander Dec - Tarrytown NY, US
Ken Suyama - Tarrytown NY, US
International Classification:

H03L 7/08
US Classification:

331 25
Abstract:

A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.