Kenneth J Barker

US Patent:

6339792, Jan 15, 2002

Filed:

Feb 27, 1998

Appl. No.:

09/032428

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC
Joseph Kinman Lee - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

709228, 709227, 713310, 713323

Abstract:

A detector and method for detecting Wakeup-On-LAN (WOL) frames in which the Wakeup field can start on a two byte word boundary (even) or in the middle of the two byte word (odd). The orientation (even/odd) of the WOL and destination address (DA) fields are determined and a first or second two byte process, depending on the orientation, is selected to analyze the frame to determine if it is valid.

US Patent:

6345310, Feb 5, 2002

Filed:

Jul 28, 1998

Appl. No.:

09/123547

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12413

US Classification:

709250, 370463, 710 2

Abstract:

A multiple port adapter having a single MAC chip with a single I/O port has reduced logic circuits and I/O pins for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end through the single I/O port to a port multiplexer and at the other end to respective storage registers. The port multiplexer is coupled to each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions through the single I/O port. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFOs to write or read data for the selected port.

US Patent:

6363076, Mar 26, 2002

Filed:

Jan 27, 1998

Appl. No.:

09/014334

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC
Joseph Kinman Lee - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 1228

US Classification:

370419, 711149, 370465

Abstract:

Methods, systems or apparatus and computer program products are provided that interface between two data buses operating at different speeds. Such interfaces utilize a buffer which has an apparent size larger than the physical size of the buffer to receive blocks of data which are larger than the size of the buffer. The apparent size of the buffer is created by simultaneously writing data to and reading data from the buffer such that the same storage locations may be used more than once to hold the data. The present invention may be utilized for receiving data from either the high speed or the lower speed bus.

US Patent:

6373848, Apr 16, 2002

Filed:

Jul 28, 1998

Appl. No.:

09/123899

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 1256

US Classification:

370401, 370428

Abstract:

A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFOs to write or read data for the selected port.

US Patent:

6393457, May 21, 2002

Filed:

Jul 13, 1998

Appl. No.:

09/114761

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC
Joseph Kinman Lee - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 314

US Classification:

709201, 709224, 370355

Abstract:

An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

US Patent:

6549960, Apr 15, 2003

Filed:

Nov 16, 2000

Appl. No.:

09/714643

Inventors:

Samuel Steven Allison - Fuquay-Varina NC
Kenneth James Barker - Cary NC
Joseph Kinman Lee - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710 29, 710 33, 710 35, 710 36, 709223, 709224

Abstract:

An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

US Patent:

6766381, Jul 20, 2004

Filed:

Aug 27, 1999

Appl. No.:

09/384689

Inventors:

Kenneth James Barker - Cary NC
Brian Mitchell Bass - Apex NC
Jean Louis Calvignac - Cary NC
Marco C. Heddes - Raleigh NC
Michael Steven Siegel - Raleigh NC
Michael Raymond Trombley - Cary NC
Fabrice Jean Verplanken - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

709246, 712 39

Abstract:

A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.

US Patent:

6870811, Mar 22, 2005

Filed:

Jan 18, 2001

Appl. No.:

09/764954

Inventors:

Kenneth James Barker - Cary NC, US
Gordon Taylor Davis - Chapel Hill NC, US
Clark Debs Jeffries - Durham NC, US
Mark Anthony Rinaldi - Durham NC, US
Kartik Sudeep - Durham NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L012/28

US Classification:

370235, 370253, 370429

Abstract:

The decision to discard or forward a packet is made by a flow control mechanism, upstream from the forwarding engine in the node of a communication network. The forwarding engine includes a switch with mechanism to detect congestion in the switch and return a binary signal B indicating congestion or no congestion. The flow control mechanism uses B and other network related information to generate a probability transmission table against which received packets are tested to determine proactively whether a packet is to be discarded or forwarded.